Discussed in 2010... see around here:
viewtopic.php?p=9829#p9829

Seems possible that (internally) register reads would happen even without chip select, and because some reads have side effects - will clear a flag - that's a misbehaviour.

Hi Ed,



Yes, I've seen that discussion, but it doesn't add any details. It actually just references wikipedia, again, as the main source without much confirmation or elaboration.




This seems to be a completely different issue than the write corruption because of synchronization issues with the address lines. As far as I can see VIA does have protection to avoid side effects when not selected. Otherwise obviously the chip will not work at all. I can't say I checked all possible cases because I didn't reverse engineer the whole layout yet. But, i.e., I can see that reading the shift register will not clear the interrupt flag if the chip is not selected. But again, there might be timing issues on systems that use a non 6502 bus protocol.

Note that as mentioned somewhere else, "read" side effects might be produced by the 6502 itself when it performs some dummy bus cycles which are assumed to be idle. But in this case the peripheral chip can't help it because the chip would be selected. This is a known issue on any 6502 platform with chips that have read side effects.

Edit: fixed wrong quoting

Yes, I was speculating a bit. It does seem like something was wrong at some point. It's not clear (to me) if it affected original pre-WDC parts, or early WDC parts.

Right now it's all speculation, and speculation won't bring us far.

If we want to know what's really going on, we need to dig a bit deeper.
This means dissecting the shift register, the related control circuitry (including flags) plus clock generation, the bus interface, and the address decoder.

My problem is that I'm not good at interpreting the diffusion layer in the microscopic chip pictures, especially when the chip was manufactured in a 2µm HMOS II process.
If I would have a polygonized images of that chip, I might be able to tear it apart within just a few weeks.
But there don't seem to be polygonized images of the 6522 in the internet.

Looks like John McMaster had made a try some time ago, but there wasn't much progress since then.
And forum member fhw72 doesn't seem to have enough free capacity to go for the 6522 soon.

I'm not speculating. I'm commenting what I see at the chip layout. I'm not ready to post full schematics yet, but I can post seudo code of the relevant logic if you want.

I think I figured out the issue about this supposed bug. The key is the Rockwell R65NC22 datasheet that has an enhancement, a fix if you want, to the bus interface. This version of the VIA latches the address lines only while the chip is still selected. Other VIA versions simply latch these signals at the clock raising edge (as every other 65XX peripheral chip).

This confirms my elaboration at the previous message. It is just about violation of the hold time specification when the address signals change before the clock raising edge. And the R65NC22 enhancement, using Chip Select to qualify address bus latching, was wrongly interpreted, or at least is wrongly described at Wikipedia. It is not that registers might be corrupted even when the chip was not selected. The wikipedia quote is inaccurate, or misleading at the very least. It should be something like this:

Register content could be corrupted if the the address lines changed, after chip select was deasserted, but before the raise of the ϕ2 clock input.

Note once again that this is not a bug at all. Exactly the same issue should happen with other 65XX peripherals, like PIA. The reason, I guess, that the mentioned "fix" was implemeted only on the VIA, is probably because VIA was commonly used on non 65XX systems.

Also note that the issue should happen on very specific, and probably not common, circumstances only. In the simple case that the write cycle is terminated too soon by the CPU, then the R65NC22 enhancement would not help because the write cycle would not be performed at all.



This is not HMOS.

If you made it that far through the chip layout, I trust you on this.


Rockwell 1987 Controller Products Databook, PDF page 83: R65NC22/R65C22 differences.
R65C22: "Register select lines are decoded during /PHI2."
R65NC22: "Register select lines are decoded during /PHI2 only if /CS2 is active low."

If you are using a different datasheet, please provide a link.

//Offtopic: 6526 is not latching the address at the rising edge of PHI2, PDF page 4.


Please provide a link\reference to this quote.


True:
Bus timing in general can be a bit tricky.
Especially when interfacing a peripheral to a CPU with a different bus interface and/or timing.
PC EGA graphics cards had used the 6845 (cousin of the 6545) or a derivate thereof.


Bus timing of the system should not violate the datasheet parameters, of course.


Good to know it's not HMOS.
//Knowing which fabrication process was used could be helpful for estimating the typical propagation delay of a logic gate within the chip.

VIA shift bit counter logic is extremely minimalist in terms of transistor count:

https://raw.githubusercontent.com/ijor/VIA6522/main/ViaShiftBitCounter.pdf

Obviously a simple binary counter is not efficient because the carry chain is very expensive. I expected a traditional 4 bits LFSR design that is normally used in these cases. Note that 9 states are required to distinguish between 0 and 8, or at least that was the design goal here. That means that 3 bits is not enough. But they actually used a simpler 5 bits shift without XOR gates that saves a few transistors. There are a total of 51 transistors in this logic.

The enable and disable signals are both active for half cycle only at the low phase of the clock. This also saves a few transitors because it avoids a dedicated pass transistor for that phase of the clock. This concept is used (some would probably say abused) on most of the chip logic.