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PostPosted: Sat Mar 27, 2021 7:05 pm 
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Hi folks, I'm starting on a game console project built around the W65C134S microcontroller. My console concept is Atari-inspired, using beam-racing techniques to control an FPGA video generator. I'd like to output 1024x768@60Hz VGA, which requires a 65Mhz pixel clock. It'd be great if I could divide that by eight to have the processor and memory running at 8.125Mhz, but the datasheet says the W65C134S is only good for bus speeds up to 8Mhz. Have any of y'all experimented pushing a little faster than the nominal limit?

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- Adam


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PostPosted: Sat Mar 27, 2021 7:18 pm 
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Welcome.

The ratings in WDC's data sheets are very conservative, and we keep finding that the parts are much, much better than the data sheets let on. When I was talking to the designer of the '134 and '265 over lunch a few years ago, he asked why there seemed to be so much reluctance to use these. I immediately said it's because the speed ratings are so much slower than those of the '02 and '816, only 8MHz. He said they might go a lot faster, but they just never tried it. Even the '816 is rated for 14MHz @ 5V, and 8MHz @ 3.3V, yet one of our members here got one going at 24MHz @ 3.3V, ie, three times the rated speed. Note of course that it's not guaranteed to go that fast; but clearly there is an absolutely huge margin. In an online interview I saw, the designer said that even in the 1970's, to label a 6502 for a given speed, it had to work at twice that speed in their manual tester; so for example for a part to be labeled 1MHz, it had to run at 2MHz in the tester, and to be labeled 2MHz it had to run at 4MHz in the tester, etc.; so if one did fine up to 3.9MHz but started having problems at 4MHz, it could be labeled for 1MHz but not 2MHz. He said they had ones running at 10MHz even in the 1970's.

Note that high temperature will slow it down, and lower voltage will too. One of the British computer manufacturers (I don't remember which one) had a design that worked fine on the workbench in their labs, but when customers ran the computers in houses with no A/C in the summer, they'd crash.

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PostPosted: Sat Mar 27, 2021 7:57 pm 
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Wow, thanks so much for the quick reply. I figured there was some tolerance in those datasheets, sounds like there's actually quite a bit! I'm reading through your website and there's lots of cool stuff there.

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PostPosted: Mon Mar 29, 2021 8:53 am 
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Welcome.

There are quite a few topics in our forum about building a FPGA or TTL based (VGA) video generator.

Since the 6502\65C02 only does consecutive write cycles in the $01xx stack area (the W65C134 microcontroller contains a 65C02 core),
my approach was to give the video controller 32kB of RAM, then to passively sniff the 6502 bus for write cycles in the $0400..$7FFF address range.
Data and address were sampled from the 6502 bus in latches, and then written/mirrored to the display RAM in the right moment.

Timing was a bit tricky, but this way it was possible to run the CPU and the video controller from different clock sources,
eliminating that need to run the CPU from a clock signal derived from the pixel clock.

Another approach would be using a IDT7008 64kB dual port RAM between CPU and CRT controller.


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PostPosted: Sun Apr 11, 2021 1:56 pm 
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You might want to choose a video resolution which is significantly higher or lower than 1024*768*60FPS.

We currently have people experimenting with 80MHz and 100MHz dot clocks and 160MHz or more is feasible for a hobbiest. 8 bits at 20MHz is suitable for 160MHz dot clock which is suitable for 2K video (1920*1080*60FPS). It is also possible to clock a 6502 at 30MHz, make FPGA exceed 70MHz or make 100MHz hardware. Unfortunately, none of them will update 786432 pixels per frame. Assuming 16*16 pixel tiles, it is optimistic for 6502 to update 640*360*60FPS without hardware assistance. This is particularly true if you wish to allocate a proportion of processing power to user input or sound.

It is possible to make something like an Atari 2600 but with 1024*768*60FPS output. Indeed, you may not require a larger address-space or additional RAM. However, the advantage over an actual Atari 2600 with scan doubler (tripler?) is marginal and it may be preferable to write games which are binary compatible with Atari 2600.

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PostPosted: Sun Apr 11, 2021 7:00 pm 
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Thanks for weighing in on my idea! I need to take some time to write up my thoughts and get some input from the community. I'll do that and create a dedicated topic thread. But here's some of the basics I'm thinking up:

- The FPGA generates 1024x768@60FPS VGA, but the display is logically 256x192@60FPS, so there is a virtual pixel clock of 4.0625MHz. The scanline generator will be writing to a line buffer so these lines can be quadrupled.

- The FPGA contains 64KB of VRAM and some hardware support for shuffling data from VRAM to sprite / playfield / character registers, so the load on the 6502 is reduced. I have some ideas for a distinctive video processor using a hand-picked 8-bit indexed color palette.

- The FPGA includes several POKEY-styled PSG cores and an FM music core.

- To make into a more well-rounded console, include a W65C265S to act as main processor, communicating with the W65C134S over a UART. Game cartridges can contain separate ROM chips for both processors, similar to NES's cartridges containing both PRG-ROM and PPU-ROM.

- Binary compatibility with previous consoles or tracker formats is low priority, but nice to have.

I'll write up a little presentation along with the somewhat unconventional design considerations for the project!

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