Welcome.
There are quite a few topics in our forum about building a FPGA or TTL based (VGA) video generator.
Since the 6502\65C02 only does consecutive write cycles in the $01xx stack area (the W65C134 microcontroller contains a 65C02 core),
my approach was to give the video controller 32kB of RAM, then to passively sniff the 6502 bus for write cycles in the $0400..$7FFF address range.
Data and address were sampled from the 6502 bus in latches, and then written/mirrored to the display RAM in the right moment.
Timing was a bit tricky, but this way it was possible to run the CPU and the video controller from different clock sources,
eliminating that need to run the CPU from a clock signal derived from the pixel clock.
Another approach would be using a
IDT7008 64kB dual port RAM between CPU and CRT controller.