I just had a great/terrible idea for an I/O channel needing no chips. Use NMI as the input, and A23 downwards as outputs. If it can bit-bang SPI, it's a winner. I'm not quite sure if it can be done. It probably means swapping out the usual latch which catches the address high bits, and swapping in a register, and that would impact the speed of the system. Or is it even worse, and only a latch will do?

Without adding any extra chips, is it legal to increase the capacity of an existing chip? Maybe that's bending the rules too much, but I'll share this idea anyway...

Another approach is to double the size of the EPROM and use the new address line as an input; ie, don't drive it as usual from the CPU. Instead, drive it from whatever external signal you want to read.

The EPROM contains two entire copies of the firmware, and the copies are largely but not 100% identical. At any point where the "input" needs to be tested, one copy of the firmware contains a BRA or JMP and the other copy simply contains NOP's (or a JMP/BRA to a different destination).

( Back in the 20th century I used this trick to get out of a tight spot -- see the "Slightly OT" section of this post. And the goal was real, not just a forum brain teaser. I wanted to upgrade an existing system, but what I was attempting seemed impossible in light of the speed that was required. )

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

It's a curious idea, but maybe there is something similar already there - the VCF 6502 Badge... It uses the IRQ as the input pin though. It's not SPI but async serial.
It uses a clever system of writes to the ROM area to implement outputs for a multiplexed display and serial output... It's not quite a "no chip" design. however...

It's a 6 chip design. CPU, ROM, RAM, 2 8-bit latches, a 74'139 dual decoder, LED display, some passives and off you go.. It could possibly be simpler if you just wanted serial and no display. (ie. just one latch and I think only half the decoder is used, so possibly lever the other half for an output bit?) Or maybe pickup *any* write to ROM area for the serial output...

http://sunrise-ev.com/6502.htm

-Gordon

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Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

(Nice ideas/examples!)

I did something akin to this for a university project.

On the Atari ST520 there was a ROM port that the memory management would allow you to read from, but not write to. Lord only knows why. In any case, I'd latch 8 of the address lines to use as byte of data out. This had the interesting effect of being able to write and read data with a single access.

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Bill