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PostPosted: Wed Aug 05, 2020 1:23 pm 
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Joined: Wed Jun 17, 2020 10:51 am
Posts: 60
Debugging writes to a 74LS574 attached to the 6502 data bus I saw these signals which are a bit different from what I would expect. Here is the clock signal:
Attachment:
clock signal.jpg
clock signal.jpg [ 85.57 KiB | Viewed 398 times ]

Channel 1 is the select line that gets triggered by writes to 0x0340. Channel 2 is the clock pulsing at 500kHz. Here is an example from one of the datalines:
Attachment:
dataline_example.jpg
dataline_example.jpg [ 72.96 KiB | Viewed 398 times ]

Is it normal that while clock signal is 0 the datalines show a slope? If not, any idea where it might come from?

thanks for any answer

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PostPosted: Wed Aug 05, 2020 2:00 pm 
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Joined: Thu Dec 11, 2008 1:28 pm
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Location: England
I think that may be as expected: with the clock low, the databus is undriven, and any TTL loads will tend to pull the signals high.


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PostPosted: Fri Aug 07, 2020 2:00 am 
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thanks

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