First: thanks to daniMolina for investigating what a 6526 timer does.

The DIA (Discrete Interface Adapter) TTL 6526 isn't meant to be a "competition" to Dani's 74HCT6526 project.


Had some time at hands, so I did schematics and PCB layouts for what I think might be "a 20MHz TTL implementation of the 6526".
Not sure, if the timers are cycle exact, and shift register and TOD might be not too compatible to a real 6526 chip.
Point is, that we don't have a dissection of the 6526 silicon... yet.
// But I wanted to have this TTL 6526 stuff off my desk before trying to aim for the SID again.

I'm sort of retired, so somebody else (Drass) would have to build and to test that hardware.


We have three PCBs:
One PCB contains two 16 Bit timers and two 8 Bit I\O ports,
one PCB contains what I think should work as TOD. //It's also a "test balloon" for the carry chain of a hypothetical 100MHz TTL CPU.
and one PCB contains the bus interface, the shift register, and the rest.


Tried to group 8 resistors of the same value together, so one could solder precision DIP16 sockets into the PCBs and plug resistor networks into them.

We have a control signal PHICEN (with a 4k7 pullup resistor), which is a HIGH_active count enable for the two 16 Bit timers,
so one could run the timers at 1MHz in a 20MHz system for software compatibility reasons.

If there is a 0 to 1 transition on the /IRQ output, for speeding up the rising edge current is injected into /IRQ for one PHI2 cycle to reduce that ghost interrupt problem.
//One might want to tinker with the value of the related resistor.

Also, if port pins are configurated as outputs, current is injected into them on a 0 to 1 transition for one PHI2 cycle,
for disabling that feature just don't plug the two related resistor networks into the sockets.
//One might want to tinker with the values of these resistors, too.

By default, if a port pin is configurated as an output, the CPU reads from the port pins.
When closing the solder jumpers on the timers_ports PCB, the CPU reads from the data output latches instead,
what might be not exactly 6526 compatible, but increases the chances that something like "INC $DC00" still works at 20MHz.

Have fun.







Edit:
A read from the status register clears the flags.
Maybe we should modify the design later to make sure that a read from the status register only clears the flags if PHICEN = HIGH...

Impressive

That is so beautiful!

And yes, I'm going to have plenty of fun with this.

Amazing work!

This looks wonderful, Dieter. Would you be able to post the schematics as gif or png files, please? Not everyone is equipped with Eagle.

Cool.

I'm reminded of a related idea from Intel, although the objective was different. Some their chips feature a parallel port that's bidirectional, but they wanted to eliminate the associated Data Direction Register that we 65xx people are used to seeing. They wanted fewer registers, possibly because that meant the chip would need fewer address input pins -- I don't recall exactly. But the goal was to have a bidirectional port with only one location which the CPU could write to and read from.

They set it up so that when a read of the location occurred it would simply return the high or low state of the IO pins.

And when a write occurred, any bit written with a 0 would output a strong, low-impedance 0 on its pin. Any bit written with a 1 didn't output much of anything. But its pin would float high (0-to-1) because they'd included a weak pullup. In this state it could act as a (weak) output or as an input! Pretty clever, except 0-to-1 transitions would be rather slow. So they included a feature that sharpened 0-to-1 transitions by injecting extra current for one cycle only.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Jeff, sorry for the delay.

Schematics are looking a bit less beautiful.
Anyhow, schematics are only documentation for PCB layouts, pretty much like C is only documentation for machine code...

Adding monochrome PNG schematics as requested.

First: bus interface, shift register, etc:

Second: timers and I\O ports:

Third: what might (or might not) work as TOD:

Project abandoned due to 2014/40/EU.