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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

There are FIFO chips with 256 to 1K entries at reasonable cost, which can be driven at full bus speed on even the faster SBC designs. Just arrange a regular clock-out from one of those, and a way to read the "full", "half full" and "empty" flags, and you no longer need to explicitly care about timing in your sample generation routine - which will make it faster.

The FIFO could be useful if I'm generating audio samples much faster than they are consumed, and want to let the CPU take breaks from audio to perform other tasks.

An idea I'd like to sketch up after work is dedicating a coprocessor to audio, that the main processor sends programs and parameters to over dual-ported RAM. The coprocessor would have IRQ and Reset controlled by the main processor while NMI comes from the audio sample clock.
The main program would copy some code into the audio processor's RAM much like shader code is sent to a modern GPU, write into a register controlling the interrupt vector and strobe IRQ or Reset to start the new program. If new programs are written to alternating buffers, changing the audio generation "shader" shouldn't have to cause audio glitches or artifacts.

When it comes to write operations to non-65xx hardware, qualification with Ø2 is de rigueur. During Ø2 low, the address bus is in a state of flux. If a write is enabled at that time it may well touch the wrong address. The 65xx peripherals understand this, but not non-65xx hardware. That's why you don't qualify 65xx peripherals with the clock.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

<I'll resist the temptation to keep going in this vein: we have other threads for discussing 6502 bus timing, and I trust it's clear that there are subtleties afoot, and there are helpful simplifications.>