Hi guys

This is more of a general PCB routing question, but I was wandering if anyone could give me their practical/professional opinion?

I've been thinking about my future higher clocked projects that I might wish to tackle and was wandering at what point would cross talk likely occur with buses? I ask as I've been looking this up and some of the 'rules of thumb' seem quite impractical - such as leaving 3 times the trace width between traces, etc. - so was wondering if I need to worry too much when running a clock, say, under 100MHz?

Any advice very much appreciated.

It depends on the distance to the ground plane, the length of the traces, and other things. See https://www.eeweb.com/tools/microstrip-crosstalk .

_________________
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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks Garth. I punched a few test numbers in:

Source rise time: 1ns
Source voltage: 5v
Length of parallel route: 10cm
Substraight height: 12 mil
Trace spacing: 12 mil
Substrate dielectric: 4

These calculate to:
Cross talk coeff: -6.02db
Couple voltage: 2.50 volts

I assume that the couple voltage is the potential voltage rise (spike) in an adjacent, parallel line?
If so then that's pretty horrible as I was going to go for 6 mil spacing and that the value then goes to 4v! .
If this is the case then I need to rethink a few designs.

Oh, one thing which didn't seem to make a difference was the length of the parallel route - tried 2cm and then 10cm - both gave the same output.

We have an entire topic devoted to high-speed construction techniques.

Crosstalk in the type of hardware we build is unlikely to be significant. Digital circuits are generally low impedance, which tends to minimize their susceptibility to crosstalk.

Of a greater concern are the effects on circuit timing and waveform distortion caused by parasitic capacitance. Hence minimizing parasitic capacitance is a fundamental consideration of PCB design. Key is planning the board layout so trace lengths are as short as practical. A good way to keep trace lengths down is to arrange the board so chips that are connected together are close together. Also, if you need gates of the same type (AND, OR, etc.) in several parts of the circuit, consider whether it would be better to use several single- or dual-gate devices instead of a larger chip—using multiple small devices instead of one or two larger ones might give you a denser layout.

Surface-mount devices, being physically smaller than through-hole, make it possible to create a denser layout. The downside is you will be working with finer lead pitch. However, SOIC (0.050" pitch) and SOJ (also 0.050" pitch) can be manually soldered, as seen below.


There are instances of people manually soldering even finer pitches...not something I have attempted.

Narrow traces can help with routing—I used 0.006 (0.015mm) signal traces in my POC units. Trace separation is not as important as one might think—a close examination under magnification of a modern PC's motherboard will reveal very tight trace separation in high frequency circuits. I use 0.025" (6.35mm) trace spacing at almost all points on my POC units, mostly as a matter of convenience. POC V1.1, which was built that way with through-hole parts, will boot at 15 MHz without the SCSI host adapter installed, and probably could run faster if I had designed in wait-stating for ROM and I/O.

The speeds of modern devices can result in ringing—a type of switching noise, which if sufficiently severe, will cause the device at the other end of the circuit to become confused. Ringing is fundamentally independent of operating frequency, which means it can be a problem even at relatively low clock rates. One of the ways you can mitigate the effects of switching noise is to build on a four-layer board, with one inner layer as ground and the other as Vcc. The two layers are effectively the plates of a large bypass capacitor, one with excellent high frequency characteristics. Four-layer construction also helps to tame ground bounce, due to the very low-impedance return path available to all devices on the board. Note that four-layer construction does not preclude the use of bypass capacitors; each chip should have one.

Anyhow, I suggest you read the above linked topic for more info.

_________________
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Hi BDD

Thanks very much for the explanation - very interesting and useful. It's good to know that cross talk is less of an issue for our types of projects.
With regards trace lengths: One thing I'm struggling with is keeping lengths down when I've got a 65C02, RAM, ROM, plus up to 4 VIAs in PLCC form and I'm having to join all of this to the busses.
Beyond keeping trace lengths down, is there anythning else I can do to reduce such capacitance?

My apologies. I had kind of forgotten to get back to this.


Yes, that seems fishy. Something isn't right. I get the same thing with only 8mm!


Note that transmission lines are a combination of capacitance and inductance. From this post:

In circuits like this with the fast edges with a lot of frequency content in the dozens [now maybe hundreds] of MHz, it's definitely low impedance and the inductance is more of an issue than capacitance when it comes to coupling (although they're both involved in arriving at the characteristic impedance of any resulting transmission line). Proof of that is that if you give a line a pulse and look at the other line, the voltage produced in the second line will change polarity if you now feed the same pulse with the same polarity from the opposite end of the first one. IOW, even though you haven't switched the polarity of the pulse in the first one, the polarity of the voltage induced in the second one depends on which end you fed the first one from. The math in the S plane is at the raggedy edge of my math abilities.

Something you can do to reduce the line lengths is to put parts on both sides, something which I have recently started to do in my work.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

It's all good and I'm grateful for any help .

I'm not entirely sure I understood about it switching polarity in nearby lines depending on the direction that a signal was sent from. Are we talking +5V fliping to -5V? Sorry if I'm coming across as a little dense on this.



That's not a bad idea. Trouble is, I was planning to use through hole PLCC sockets for easy part replacement. However, I could try this with just one project to see how it turns out.

Cheers!

Let's say you feed a positive pulse into wire (or trace) A. Whether the resulting induced pulse showing up in wire B will be positive or negative will depend on which end you feed wire A from. I might draw a diagram later. Right now I need to get to bed.


That does make it a bit difficult. SMT is most conducive to this; but you can do it with thru-hole parts to some extent also, by staggering the rows (planning how you'll assemble it in the right order, since you can't solder under an IC that's already there), or you can do what's called a "butt" or "I-lead" which is where you trim the DIP's leads just below the shank and put them down on pads without holes and form a solder fillet that holds the lead to the pad.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Fundamentally, what's happening is that to get a voltage change from one end of a track to the other, you need to send a short burst of current along it (due to parasitic capacitance). This in turn produces a small magnetic field around the track as it flows (due to parasitic inductance), the flux (change) of which tends to impede the desired flow of current. The inverse process can occur in nearby tracks, like a really weak and badly shaped transformer: magnetic flux -> induced current -> voltage change.

Consider two parallel tracks connecting pins A-B and C-D. We'll assume the C-D track (an address line) is quiescent, driven to either level from C and observed by D. The A-B track (on the data bus) may be driven in either direction. The important events here are a rising edge from A, a falling edge from A (in both of which B is tri-stated), a rising edge from B, or a falling edge from B (in both of which A is tristated). Merely changing which end of the bus is driven doesn't do anything, provided both are driving the same level at that time.

You can then see that a rising edge from A causes an opposite current to a rising edge from B, even though it causes the same change in voltage on the A-B track. Thus the magnetic flux will also be reversed, as will the current induced in the C-D track. But since the C-D track is still driven in the same direction, the voltage observed at D will change in the opposite sense.

Most of the signals in a 65xx system will have slow enough transitions and enough settling time between any change and the levels taking effect that crosstalk is not of much concern. For faster signals sent over longer distances, as found in modern PCs, resistive impedances are deliberately introduced to damp out crosstalk and reflections.