I got my SDC_One computer with 65C816 working properly so I tried to use M and X status for disassembly of instructions by hardware monitor. Some interesting findings:
1. WDC datasheet contains some fun stuff regarding the timing. From the datasheet it looks like we have a time machine hidden inside - 65C816 changes the status few nanoseconds before it detects a clock edge, which cannot be true. Of course the E and M/X pins state changes soon AFTER the clock edge and its valid before and during the next edge, guaranteed for tEH. tES looks like a mistake in the docs - it should be replaced by tEV - time from clock edge to status becoming valid.
2. E output changes from 1 to 0 in the middle of the next opcode fetch cycle after completion of XCE. It changes from 0 to 1 in the middle of the next (idle) bus cycle after XCE opcode fetch.
3. M changes in the middle of the next opcode fetch cycle, so it may be used for argument size determination during disassembly.
4. X changes at the beginning of the first cycle AFTER the next opcode fetch which makes it impossible to use it for proper disassembly of instruction's arguments in advance - when the opcode is fetched, X still holds the old value.

Please forgive my possible ignorance, but how does the execution of an instruction relate to the disassembly of same? Aren't the pins going to reflect the state of your disassembler code, rather than the code it is trying to disassemble?

Mike B.

More info on SDC_One can be found here:
viewtopic.php?f=4&t=5053

It's the hardware monitor running on STM32 which does the disassembly stuff while supplying the CPU with data (opcode in this case).
BTM I get something like 420.000 bus transfers per second with 65C816 and 520k transfers/s with 65C02 (simpler bus protocol, no bank and status handling).