Update on the project, explaining how we'd get round the patent issues:
It'll likely be done in a mixture of Cadence OrCAD, Icarus Verilog and/or Synopsys software, with additional libraries either freely downloaded or bought from Mentor Graphics, GlobalFoundries, TSMC, IBM and/or these companies. Any thoughts from those here?
This CPU, if the design works right, the streams of x86 CISC instructions can be ganged into massive 512-bit wide macro-operations, and it isn't horribly bugged like *cough* current Intel CPUs with their kernel memory sapping/SYSCALL privilege escalation flaw, should perform between 4-40x (!!!) better in singlethreading applications, albeit with a large die size (>600mm^2 for 8 cores) and perhaps low clock speed, on a modern 14nm process, and the first ones off the factory line will sell for over $500,000 a piece. To get around copyright and patent issues, we will strike contracts with AMD and VIA to license the x86 technologies.
This means Passmark singlethreaded scores of over 80,000, Cinebench scores of 300,000 or more and no more excuses for people claiming their CPU is bottlenecking their graphics card.
The CPU ID will most likely look like this: CertifiedCBR or CertifiedCTN 801486-class 8 core(s), 16 thread(s) Model 0 Family 0 Stepping C0 Extensions supported: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, VIA 64, VT-x, AES, AVX, AVX2, AVX-512, CVT16, FMA3, FMA4
Any thoughts on the overall idea? And yes, I will hopefully soon be looking at simulating a full 8086 system in Icarus Verilog or perhaps tweaking an existing design, from, say, OpenCores. At the moment I'm working as a tester on the 86Box PC emulator project, and have looked over large parts of its code including the CPU dynamic recompiler.
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