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PostPosted: Sun Jun 19, 2016 6:51 pm 
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Dr Jefyll wrote:
BigDumbDinosaur wrote:
Well, I am ex-Navy. :) :D 8) :lol:
Is that why in that thread last week you were trying to convince us that during VPA=VDA=0 those '816 control signals were FLOATING ? :wink: <groan>

Man overboard!!! :lol:

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PostPosted: Sun Jun 19, 2016 6:54 pm 
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From my RS-232 primer: "If the speed of the transmitter and receiver disagree by more than 2-3%, the errors will start showing up. 5% would be a half bit time by the end of the frame. If the transmitting end were 1% below the intended speed and the receiving end were 1% above the intended speed, you would have just about all the error the system could tolerate and keep working reliably under ideal conditions."

Happy Fathers' Day to all the fathers. Both our sons and our daughter-in-law , plus my parents, will be here in less than an hour.

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PostPosted: Sun Jun 19, 2016 7:09 pm 
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BigDumbDinosaur wrote:
The NXP 28L92 I am currently using in POC V1.1 can be configured for either an Intel or Motorola bus interface. Ironically, the Intel interface proved to be less a hassle to adapt to the 65C816.
For anyone who's wondering, "Motorola bus interface" could mean two things, both distinct from the Intel approach. The Motorola 6800 bus matches that of the 6502, but the Motorola 68000 bus is something else entirely. I remember getting momentarily tripped up by this ambiguity, perhaps in a datasheet from NXP; I don't recall.

BigDumbDinosaur wrote:
your baud rate clock should be either 1.8432 MHz or 18.432 MHz
[Edit:] Integer multiples of the exact rate do eliminate error, but 10X 1.8432 MHz isn't the only option -- you can go 3X or 5X the 1.8432 MHz, for example, and still have zero error.

BTW and FWIW, the SC16IS750 I'm playing with accepts rates up to 80 MHz on its 16X input clock. At that rate you get pretty fine resolution, so even if the math won't allow you to get your exact desired rate, you're bound to have an error that's darn small. A degree of error is tolerable anyway, as Garth noted. But running a higher input clock lets you do slightly better, FWIW.

srowe wrote:
Latching /ADS from /IO2 and Φ2 ORed together gives me reliable register reads.
I don't find your meaning clear, I'm afraid. Any chance you can post an up dated schematic, please?

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Last edited by Dr Jefyll on Sun Jun 19, 2016 7:30 pm, edited 2 times in total.

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PostPosted: Sun Jun 19, 2016 7:19 pm 
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Dr Jefyll wrote:
BigDumbDinosaur wrote:
The NXP 28L92 I am currently using in POC V1.1 can be configured for either an Intel or Motorola bus interface. Ironically, the Intel interface proved to be less a hassle to adapt to the 65C816.

For anyone who's wondering, "Motorola bus interface" could mean two things, both distinct from the Intel approach. The Motorola 6800 bus matches that of the 6502, but the Motorola 68000 bus is something else entirely. I remember getting momentarily tripped up by this ambiguity, perhaps in a datasheet from NXP; I don't recall.

Right you are; I should have clarified that. The "Motorola bus" in this case means the 68000, not 6800, something that NXP doesn't explicitly state in the data sheets.

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PostPosted: Sun Jun 19, 2016 8:03 pm 
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Dr Jefyll wrote:
srowe wrote:
Latching /ADS from /IO2 and Φ2 ORed together gives me reliable register reads.
I don't find your meaning clear, I'm afraid. Any chance you can post an up dated schematic, please?


Sure.

Attachment:
rs232-bw2.png
rs232-bw2.png [ 11.71 KiB | Viewed 987 times ]


Looking at the VIC-20 schematic again I was incorrect to say the expansion address is only valid when Φ2 is low. I still don't know why the original circuit doesn't work.


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PostPosted: Sun Jun 19, 2016 8:19 pm 
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Thanks. What are you using as a reference for the VIC-20 signals -- can you post something, or provide a link?

srowe wrote:
I still don't know why the original circuit doesn't work.
Neither do I, but we know Andrew's circuit which you linked to does. That was your starting point, but it failed. The explanation probably has to do with what the VIC-20 puts between its 6502 and the expansion port.

Footnote to the logic-level discussion: your original circuit should've used 74HCT00, not 74HC00. But it's not the sort of mistake that guarantees failure. Sometimes stuff that shouldn't work does. (Erratically, perhaps.)

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PostPosted: Sun Jun 19, 2016 8:42 pm 
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Dr Jefyll wrote:
Thanks. What are you using as a reference for the VIC-20 signals -- can you post something, or provide a link?


I use this schematic (or an original paper version of it) http://www.mainbyte.com/vic20/e_schematic.pdf along with various paper and PDF books (VIC-20 Programmer's Ref, Vic Revealed).


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PostPosted: Mon Jun 20, 2016 7:55 pm 
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IO2 you connect to ~CS2 is,gates with PHI2. I would rather connect ~CS2 to ground. It is sufficient to have dedicated RD and WR to select the device.


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PostPosted: Tue Jun 21, 2016 6:12 am 
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Thanks for the suggestion I'll give it a try.


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PostPosted: Mon Jul 04, 2016 11:28 pm 
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Could the terminal be transmitting a continuous break character when there is nothing else to transmit ?
Would it be necessary to have to filter out break characters in the receiver ?
(Assuming there's no CTS/RTS hookup).

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PostPosted: Sun Jul 10, 2016 8:51 pm 
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I've now got the board stable at 9600 now. The driver code is nearly complete, just need to handle dropping RTS when the receive buffer is nearly full. I did have some problems with the MODEM Control Reg, reading it doesn't seem reliable, sometimes bits seem to flip which causes problems when toggling the LEDs I've attached to /OUT1 & /OUT2. I've used a zero page byte to store the authoritative state. No other register, including the Scratch Reg seems to suffer from this.


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