There's not much current going through the signal traces, and they are short anyway, so a little bit of resistance doesn't cause any harm. Power is distributed by the power plane, so that's not a problem either. A few other non-signal traces, such as the MAX238 charge pump connections, can be done with thicker traces.

Eagle also allows you to enter the board house limits in the design rule checker (and save it as as a .dru file) so you can verify that the design doesn't have any design rule violations. This is highly recommended.

Maybe it would work to have the CPU bus run left to right, and put the signalling components above that. Although I'm guessing that at this point you have no interest in redoing all the work.

Believe me when I say that the idea of having to redo the board sort of cracks me down the middle, but I'd rather get this right and learn from the experience.

So... would you run all the buses across the board from the CPU and then have the RAM and EEPROM etc sit above or below the buses?

If the DIPs are given .030" holes, you can use .050" pads, leaving .050" between pads, which gives room for two .010" traces or three .007" or .006" traces. I always try to make the layouts so there's no bare-board space between parts, and from the top you can essentially only see the board around the edges; but that's just me, largely because of my work always requiring maximum density.

A .008" 1oz trace can handle a half amp with a 20°C rise. (2oz copper is common on the outside layers of thru-hole boards if your minimum trace/space is .010".) 1oz copper is .0014" thick, and skin effect won't really come into play at our frequencies; but if line line is enough to matter, then you calculate trace width to give the desired transmission-line impedance for the particular separation you have between the signal layer and the ground plane, whether .020" or whatever, and the dielectric constant of the board material (which is 4.1 for the common FR-4 PCB material).

BTW, I never use a grid when laying out PCBs. I also don't confine trace angles to 0/45/90°. I let them go at whatever angle makes for best density, least crosstalk, etc..

BTW #2: Looking at my high-density PCB-design book to review a couple of the facts above, I am reminded that if you run into a number-of-holes limitation in the PCB manufacturing service you plan to use, you can solder DIPs down to pads on the board without using holes. It's called "butt" or "I lead," and the pads are typically .050"x.100", and you make a solder fillet where the lead meets the pad. (That pad size is for automated assembly with solder paste. You can probably reduce the pad size if you're soldering by hand with a small iron.) The "butt" or "I lead" method may also jack up the IC far enough off the board that you can put other smaller ICs underneath it. (Another way to jack up the IC and leave room underneath is to use socket rows.)

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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Eagle has no real time DRC so trying to get maximum routing density without a grid, or with irregular angles is very hard. With a grid adjusted to the allowed spacing it is a lot easier.

No, I was thinking about putting CPU, RAM, EEPROM, VIA (i.e everything connected to the big buses) all vertically, side by side, with the buses running horizontally between the pins, and then put all the other stuff above that. But I have little experience routing these DIP parts, so I'm not sure it will actually work.

As far as trying to "perfect" the design, keep in mind that it is good enough if it works, and you can most likely achieve that by using thinner traces on the current layout, and finding a way to squeeze the last couple in.

You may also benefit from the knowledge that your SRAM doesn't care about the ordering of the address and data signals, which may allow you to rotate it 180° in relation to the other large DIPs ... it could in some cases be enough to make a routing more efficient. I even went further than that on one of my old breadboard experiments, and reversed the data lines on my PIA and SRAM to make the wires shorter. My software had to account for the reversed bits when it accessed the PIA's control register, but it worked great.

Mike B.

Better to enable the RAM when a valid address is present on A0-A15. You are throwing away quite a bit of setup time by waiting until after the rise of Ø2 to enable the RAM.

What you do want to qualify with Ø2 are the read/write signals seen by the SRAM. Qualifying read isn't essential with the 65C02 but qualifying write is, since the data bus may contain random content while Ø2 is low.


The above circuit will work with any 65xx MPU and any RAM or I/O device that has separate /RD and /WD control inputs. It is not to be used with 65xx I/O devices.


That is essentially how I am doing it in POC V2.


In the above illustration, the 65C816 (PLCC-44) is at the right. To the left of it is the SRAM (an SOJ-36 package), then the EPROM, then the "expansion socket" and finally the QUART (PLCC-52). The CPLD (PLCC-44) is immediately above the SRAM and EPROM socket. Signal traces are 6 mils and signal via are 26 mils with an 8 mil hole.

The theory behind this layout is that the device with the most number of bus connections, the SRAM, is closest to the MPU and the device with the least number of bus connections, the DUART, is farthest from the MPU. Trace routing tends to get easier this way. I used the same layout approach in POC V1, which is stable at 12.5 MHz, and a bit wobbly at 15 MHz.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

So BTW #3: I don't use any DRC, realtime or otherwise. I'm always looking at the X/Y display and measuring the room between things though, and frequently reaching for the calculator to make sure I have adequate clearance, especially when a trace has to pass by a pad at odd angles. The only DRC my CAD has is non-realtime, and it gives thousands of supposed DRC violations because it doesn't understand the unorthodox stuff I'm doing, which is why I don't use it. I've done many dozens of very dense boards over the years though that came out right on first try, with no production problems.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The RAM is fast and the clock is slow, so there's enough setup time left. Why make it more complicated than it has to be?

Sounds like tedious work. How long would it take you to route a board such as banedon posted earlier in this thread ?

*lightbulb moment*

This is really useful to know. I had not considered this trick, despite having laid out several SBC boards and numerous breadboards. I believe SRAM/[EEP]ROM pinouts are defined, and thus at least memory device bus pins are orientated the same direction, but this would probably have saved me some work switching directions on databus pins relative to the CPU. Cool! Unfortunately my current board is 99% done, but it's great to know for the next one.



This is possibly taking it a step too far for me. My head would start to hurt.



I find grids, and fixed angles, useful. How do you keep bus traces equidistance without a grid?



Yes, I could not work like that either. I went from gEDA "pcb", which has a manual DRC report to KiCADs continuous enforcement and I would not want to go back. Yet alone not having a DRC at all...

Is anyone aware of any books (or online guides, I guess) that cover PCB design techniques?

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Nor do I. All of my boards are 100 percent manually laid out. I seem to have an innate sense of how things will fit and where they will go.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

The RAM may be, but what about ROM?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Only the RAM CS is qualified with phi2.