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JimDrew
 Post subject: 6522 IRF and IER
PostPosted: Tue Aug 11, 2015 9:11 pm 
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Posts: 107
Does anyone know the answer to this: If an IER bit is not enabled and a corresponding interrupt occurs (such as CA1), do the IRQ and/or IRF bits get set anyways? Is it possible to poll these?

Thanks!
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GARTHWILSON
 Post subject: Re: 6522 IRF and IER
PostPosted: Tue Aug 11, 2015 9:33 pm 
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If a bit in the VIA's IER is clear, the corresponding bit in the IFR can be set but it will not result in IFR7 being set, nor will it pull IRQ\ down. I just tried it on my workbench computer. The latter especially makes sense, since polling multiple 65xx I/O ICs to see who caused the interrupt would initially be done with BIT IFR and branching on bit 7. Then if you find the bit 7 was set, you would further examine that IC to see what caused the interrupt. Normally you would know what to test, and there's no sense in testing for interrupts you did not enable in the IER; but if you had to, you could AND the IFR with the IER so non-enabled interrupts don't show.

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JimDrew
 Post subject: Re: 6522 IRF and IER
PostPosted: Wed Aug 12, 2015 4:11 pm 
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OK, so the IFR bit can be set, even though the IER bit is cleared. This means you could poll the bit if necessary (although as you say, bit 7 would not be set). I needed to know this for emulating the 6522 in software. Thanks!
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JimDrew
 Post subject: Re: 6522 IRF and IER
PostPosted: Sun Aug 23, 2015 4:06 pm 
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OK, after some experimenting I have figured out something that is not detailed in any of the datasheets (MOS, WDC, Rockwell). If the IER bit of a corresponding IRF bit is not set, then bit 7 (IRQ) of the IRF will NOT be set. The IRF bit itself will be set and that's it, not affecting the state of the IRQ output.

What I can't tell is what happens when you clear the IER bit when a IRF bit (and IRQ) are set. Does the IRQ get cleared even though this event already occurred?
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BitWise
 Post subject: Re: 6522 IRF and IER
PostPosted: Sun Aug 23, 2015 5:22 pm 
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JimDrew wrote:
What I can't tell is what happens when you clear the IER bit when a IRF bit (and IRQ) are set. Does the IRQ get cleared even though this event already occurred?


If you clear an IER bit then the corresponding IFR bit will not contribute to generating an IRQ but the condition itself if not cleared. You have to reset the flag or access the appropriate register (e.g for timer flags) to clear the condition.

For example in my SXB interrupt handler
Code:
                lda     VIA1_IFR                ; Is VIA1 the source?
                bpl     VIA1Handled             ; No.

                pha
                and     #%01000000              ; Is Timer1 the source?
                beq     VIA1T1Handled           ; No
                lda     VIA1_T1CL               ; Clear the interrupt

                inc     JIFFY                   ; Bump jiffy counter
                lda     JIFFY
                cmp     #TIMER_HZ               ; Reached a second?
                bne     VIA1T1Handled           ; No.

                stz     JIFFY                   ; Reset jiffy counter
                inc     TIME+0                  ; And bump main timer
                bne     VIA1T1Handled
                inc     TIME+1
                bne     VIA1T1Handled
                inc     TIME+2
                bne     VIA1T1Handled
                inc     TIME+3
VIA1T1Handled:

                pla                             ; Is Timer2 the source
                and     #%00100000
                beq     VIA1T2Handled           ; No.
                lda     VIA1_T2CL               ; Clear the interrupt

                lda     #%00100000              ; Disable T2 interrupt
                sta     VIA1_IER
                lda     #TX_LOCK                ; Unlock TX hardware
                trb     LOCKS
VIA1T2Handled:

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