Don't know if what I wrote inspired you to look into some of the configuration characteristics of your FPGA, but it's good to know that the Altera part offers similar signals to the Xilinx. I have become very accustomed to the Xilinx configuration mode signals, and would not consider moving to the Altera products unless they offered a similar capability. Thanks for posting about the similarities between these two FPGA families.
The Xilinx products allow you to change the cycle in which Done is asserted during the configuration sequence as part of the bitstream. The normal settings have Done asserted before all of the internal configuration functions are completed. So I manually configure the Done signal to assert after all of the other configuration operations have been completed. Since it appears that you have some manual control of some of these signals in your FPGA bitstream generator, look around in that tool for a way to change when CONF_DONE is asserted; I have to edit the settings for DONE in the Xilinx bitstream generator.

_________________
Michael A.

I'm on the bus until tomorrow so I can't draw a schematic but I will try to explain. SRAM OE has two inputs. One of them is from the 74HC244 buffer and the other is from a pin on your FPGA. When the system starts, the FPGA pin is floating and the 74HC244 immediately drives the line high to z-state the SRAM OE. The OE pin of the 74HC244 also has two inputs, a pull down and an FPGA pin. Because that FPGA pin is also floating on startup, the pull down enables the OE of the 74HC244, which drives the SRAM OE pin high. After your FPGA is done configuring, the FPGA pins driving the SRAM OE and the 74HC244 OE can now be driven by the FPGA. Bringing the 74HC244 OE high z-states the 74HC244 pin driving the SRAM OE since it is now can now be driven by an FPGA pin.

EDIT: Sorry for the poor quality. Try this:


At start up the 74HC244's OE is 0 and the SRAM OE is driven high by 1Y0. After configuration, IO1 drives the 74HC244's OE high, which z-states 1Y0. the SRAM OE is then controlled by IO2. If you are afraid you will make a mistake with the FPGA configuration, you can add a resistor to 1Y0 to prevent contention, but you won't need one otherwise.