Hi guys

I've managed to get my 6502 build to run at 10MHz with some stability now. The clock wave form looks quite distorted - but then again this seems to happen at lower frquencies as well.
Is this normal?
My own knowedge says that it's fine as long as you get the amplitude and a general (-ish) square wave, but I don't have a huge amount of experience so thought I'd ask. I'm especially curious about the M-like shape of the wave.

Some of that could be due to your test rig. In order to accurately reproduce a 10 MHz square wave, the probe should be good to at least 100 MHz. Ditto for the 'scope.

Also, it's likely that your circuit is producing some ringing, which you may be able to suppress with some resistance to ground at each end of the signal path. As long as the signal makes a clean transition through the affected device's "no man's land" switching characteristic, you should get proper operation.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Thanks for the reply, big D. The scope is an Owon PDS5022S and rated at 25MHz. Not sure about the probes, but as they came with it I suspect they are the same (got it all second hand and for free so no complaints there ). So you might be right, especially as considering that the following screen shots show things looking more and more distorted from 4MH to 10MHz (I've heard that increased/decreased frequency should have no effect on ringing in and of itself?). I would have included more, but I only have a 4, 8 and 10MHz crystal osc can at the moment.

One thing to say is that I don't really have a ground plane set up as I didn't quite understand Garth's article (a failure on my part!). I've been trying to find a visual demonstration of a star ground plane. I suspect its lack may contribute to this kind of thing.

4MHz


8MHz


10MHz

When you say resistance to ground, are you speaking about putting resistors between ground and, say, the address and data bus (as I noted that the BBC Micro did in this post:
http://forum.6502.org/viewtopic.php?f=4&t=2960)? If so, is it just a case of pulling the clock line to ground through a 6k8 resistor? I've never seen this with the clock so suspect that i've misunderstood.

Banedon,

Your waveforms show the typical results of a 'scope with insufficient bandwidth - especially the 10MHz trace where the third harmonic is clearly visible as the humps on the top and bottom of the square wave. Also, the slow rise and fall on the wave edges is another effect caused by insufficient scope bandwidth - the lower the scope bandwidth, the slower the rise and fall of the edges of a pulse will appear on the scope. Truely vertical pulse edges require a theoretically infinate bandwidth to display properly!

As your circuit is working correctly, the poor shape of the pulses on your scope is almost certainly a reflection of the limitations of your oscilloscope. The pulses in your circuit are probably much cleaner and faster than your scope displays.

Even if the pulses in your circuit were as poor as they are shown on your scope, they would be absolutely fine for driving a 65C02 clock input as this has a schmidtt trigger input and the ripple on the tops and bottoms of the pulses would be ignored. The 65C816, on the other hand, doesn't have such a nice clock input and requires much higher quality clock pulses.

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Shift to the left,
Shift to the right,
Mask in, Mask Out,
BYTE! BYTE! BYTE!

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks for your responses, guys. I'll have to start looking around for a 100MHz+ 'scope. I was thinking perhaps the Owon SDS7102.

With regard to the probes - definitely in the x10 mode .

I'll look at putting in a star ground plane, although do you happen to have a diagram of one? I'm imagining the grounds for all ICs/devices coming into the centre under the board? Not sure.

While I'm here, a quick question with regard to speed? How does the 6502 deal with speed increases with respect the RAM and ROM ICs? I.e. I've increased the speed on my project from 2MHz to 10MHz and this is within the limits allowed by the CPU and VIA (both WDC parts with a max of 14MHz). I assume that the RAM and ROM are accessed at an appropriately increased speed? If so, this may explain why I was having trouble at 10MHz: I was at random times having rubbish appear on my LCD. As soon as I swapped the RAM (an HY62256B LLP-70) for a Toshiba TC55257DPL-70L it was fine. I.e. although they both run at the same speed, the Toshiba part is coping with the faster access than the HY62256B as it's getting borderline out of spec (too slow for what's needed)?

Resistance to ground is one method, Thevenin termination is another. Still another is the use of a Schottky diode, with the anode connected to ground, that is, reversed biased. Try it first with resistance to ground and see how that goes. Have you read this topic?

Ringing comes from signal reflections on the affected line that are triggered by very abrupt changes in voltage level, especially if the theoretical propagation time of the signal path is a significant fraction of the signal transition time. The clocking frequency itself is usually not the culprit—a low frequency signal may trigger ringing if the state transition time is extremely short. The more rapidly a device can change its output state the greater the likelihood of significant ringing.

Ringing is especially likely when using 74AC or 74ABT logic, or if driving signals with a CPLD or FPGA, due to the very rapid switching speeds such devices are capable of attaining. I get a little ringing on Ø2 with POC V1.1, despite a not-inconsiderable amount of effort to keep that line as short and direct as possible. Ø2 is derived from a 74AC74 flip-flop that is driven by the clock oscillator, and that flop has single digit nanosecond transition time from one state to the other. I'm not concerned with it, as the crossover from one logic state to the other is clean and the circuit will work okay at 15 MHz.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

It sounds as though you may be violating the timing of your RAM and ROM.

The -70 in their part numbers refers to the maximum guaranteed time in nanoseconds in which they will respond to selection and read- or write-enable without error. This number is a guarantee, but oftentimes parts will be faster than advertised. However, you cannot bank on this being the case. Performance will also be affected by operating temperature and voltage, as well as slight differences in the die, which explains why one RAM works okay and the other doesn't.

The key to understanding why your machine occasionally produces "rubbish" (I like that term in a computer context ) on the display is in comparing the RAM's guaranteed performance to the machine cycle time. At 10 MHz, the machine cycle time is 100ns. However, the actual time in which it is possible for the 65C02 to access a device is less than that, as can be seen by studying the MPU's timing diagram. Also a factor is the propagation delay caused by the glue logic and by parasitic capacitance and lead inductance. When all is said and done, the actual time during which the RAM has been selected and can be reliably read and written may be less than that 70ns rating, causing random errors.

In designing your circuit with a specific speed in mind, you have to analyze the timing of the slowest device on the bus (usually a ROM) and compare it to the time that will elapse from when the MPU presents a valid address and RWB state until the appropriate chip select has been asserted and an appropriate read or write signals is applied to the addressed device. You then add to that time the amount of time the addressed device will take to react to the chip select and the read or write signal—response to chip select is usually a bit slower than response to an /RD or /WD signal. If that sum exceeds the device's rating you will be violating its timing and can expect errors.

With a 65C02 (or 65C816), the data bus is not guaranteed to be "valid" until the rise of Ø2, which means that the time in which the addressed device will see usable data during a write cycle will be one-half a machine cycle, or 50ns at 10 MHz. Similarly, during a read cycle the 65C02 samples the data bus at the fall of Ø2, which means the addressed device has to be sure it is driving the data bus before the fall of Ø2.

Succinctly stated, setup should be initiated as early as possible during Ø2 low so that as much of Ø2 high as possible can be used to read or write. If the device cannot respond before the next fall of Ø2, errors are likely, producing "rubbish" on the display, among other things.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

@banedon: How is your current build constructed?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

The 0V and +5V rails are along one edge of the PCB and look a bit horrid due to it not being wire-wrapped and so a bit of a solder blob due to the amount of connections (my PCB does not have tracks, but single pads making things a bit difficult). The VDD/VSS connections from the various ICs generally go straight to those two points. So in a way, I have created a star ground plane – although a very lopsided one! . I've attached a picy below:


My next version will be to use Garth’s idea of using a wire wrap DIL socket in the centre which will avoid long VCC/VSS wire lengths and to use thicker wire for those connections.