Recommendations for a ROM chip that will work at 10Mhz?

[LIV2]

Hi

I've been working on my own 6502 based computer and am wondering what is the best rom to use?

I was thinking AT28C64B but after seeing that the read time is 150ns I'm lead to believe this would limit me to a clock frequency of about 3mhz?

[BigEd]

There may be a fast ROM, but note that many designs will operate at varying clock speed, or use RDY to introduce wait states, so they can use slow ROM and also run full speed with fast RAM. The same applies to peripheral chips - you may need to slow down to talk to them.

Cheers
Ed

[GARTHWILSON]

I haven't shopped for (E)EPROM in years, but EPROMs (starting with 27, not 28, and requiring a UV eraser to erase them) were commonly available down to 55ns, and, on rare occasion, 45ns.

[clockpulse]

LIV2 wrote:

Hi

I've been working on my own 6502 based computer and am wondering what is the best rom to use?

I was thinking AT28C64B but after seeing that the read time is 150ns I'm lead to believe this would limit me to a clock frequency of about 3mhz?

I have an SBC running stable at 10mhz and it uses two of those devices. The 150ns rating is MAX, they don't give a typical rating. It's 'typically' faster than 100ns. Make sure to enable the chip address decoding early in phase 1, and as long as the chip's output is stable before the end of phase 2 it should be fine.

[BigDumbDinosaur]

LIV2 wrote:

Hi

I've been working on my own 6502 based computer and am wondering what is the best rom to use?

I was thinking AT28C64B but after seeing that the read time is 150ns I'm lead to believe this would limit me to a clock frequency of about 3mhz?

I use AMD's 27C256-55 EPROM, which is a 55ns device. It is functional at 12.5 MHz without wait-stating. Be sure to heed clockpulse's advisory about enabling it during Ø2 low. In other words, do not qualify its chip select with Ø2 (also applies to other chips, not just EPROMs). You can get it from JAMECO electronics.

[LIV2]

Awesome, thanks guys!

I've modified my board design now to remove the qualification of the rom's chip select by Ø2 now.

So for other things that don't need Ø2 qualification, that'd be things like the ACIA/VIA etc yeah?

[GARTHWILSON]

Quote:

So for other things that don't need Ø2 qualification, that'd be things like the ACIA/VIA etc yeah?

not only don't need them, but must not have them.

[BigDumbDinosaur]

GARTHWILSON wrote:

Quote:

So for other things that don't need Ø2 qualification, that'd be things like the ACIA/VIA etc yeah?

not only don't need them, but must not have them.

To clarify what Garth is saying, the 65xx support chips (6521, 6522, 6551) must have all control inputs, meaning RWB, chip selects and register selects, valid before Ø2 goes high. Otherwise, they will not respond. RWB should be directly connected to RWB on the microprocessor, Ø2 on the device should be directly connected to Ø2 on the microprocessor, and the glue logic that selects the device must do so without qualification by Ø2.

Use of Ø2 to qualify chip selects seems to be lamentably common in 6502 hobby systems, and is incorrect design practice. In all 6502 family microprocessors, the address bus goes valid about midway through Ø2 low, at which time glue logic should enable the appropriate chip select. In the case of the 65C816, the address bus goes valid during Ø2 low and when VDA and/or VPA go high. If both VDA and VPA are low then the address bus is invalid.

Reads and writes to non-65xx peripheral devices should be qualified by Ø2, as the data bus is not guaranteed to be valid until after Ø2 goes high. In particular, enabling a device's write input during Ø2 low could cause data corruption in RAM or a write to the wrong register in an I/O device. In the case of the 65C816, the data bus emits the bank addressing when Ø2 is low during a valid memory cycle. Therefore, reads during Ø2 low must be inhibited to prevent bus contention.

[GARTHWILSON]

BigDumbDinosaur wrote:

GARTHWILSON wrote:

Quote:

So for other things that don't need Ø2 qualification, that'd be things like the ACIA/VIA etc yeah?

not only don't need them, but must not have them.

To clarify what Garth is saying, the 65xx support chips (6521, 6522, 6551) must have all control inputs, meaning RWB, chip selects and register selects, valid before Ø2 goes high. Otherwise, they will not respond. RWB should be directly connected to RWB on the microprocessor, Ø2 on the device should be directly connected to Ø2 on the microprocessor, and the glue logic that selects the device must do so without qualification by Ø2.

<thumbs up>

Quote:

Reads and writes to non-65xx peripheral devices should be qualified by Ø2, as the data bus is not guaranteed to be valid until Ø2 goes high. In particular, enabling a device's write input during Ø2 low could cause data corruption in RAM or a write to the wrong register in an I/O device.

Actually, the 65c02 is not guaranteed to put valid write data on bus until tMDS (25ns in current-production WDC 65c02's) after phase 2 rises. It's not a problem though, as long as the address is correct and any invalid data gets fixed in time for the device's data set-up time.

[BigDumbDinosaur]

GARTHWILSON wrote:

BigDumbDinosaur wrote:

Reads and writes to non-65xx peripheral devices should be qualified by Ø2, as the data bus is not guaranteed to be valid until Ø2 goes high. In particular, enabling a device's write input during Ø2 low could cause data corruption in RAM or a write to the wrong register in an I/O device.

Actually, the 65c02 is not guaranteed to put valid write data on bus until tMDS (25ns in current-production WDC 65c02's) after phase 2 rises. It's not a problem though, as long as the address is correct and any invalid data gets fixed in time for the device's data set-up time.

That was supposed to say "...until after Ø2 goes high." I type faster than I think, so words sometimes get lost in the process.

The 65C816's spec for tMDS is 30ns maximum. As with some of the other timing values listed for the '816, that number is suspect. If 30ns were true and Ø2 were 14 MHz, there would be only 5ns before the fall of Ø2, leaving the addressed device scant time to fetch from the data bus. Attempting to run the '816 at 15 MHz or faster would mean that tMDS will never be met, since the fall of Ø2 would occur first. However, the CMD SuperCPU cartridge ran its '816 at 20 MHz, which is a 25ns half-cycle time By all accounts, that cartridge was very stable, which implies that tMDS is no more than 20ns or thereabouts, which is still cutting it real close.

[cr1901]

BigDumbDinosaur wrote:

GARTHWILSON wrote:

Quote:

So for other things that don't need Ø2 qualification, that'd be things like the ACIA/VIA etc yeah?

not only don't need them, but must not have them.

To clarify what Garth is saying, the 65xx support chips (6521, 6522, 6551) must have all control inputs, meaning RWB, chip selects and register selects, valid before Ø2 goes high. Otherwise, they will not respond. RWB should be directly connected to RWB on the microprocessor, Ø2 on the device should be directly connected to Ø2 on the microprocessor, and the glue logic that selects the device must do so without qualification by Ø2.

Use of Ø2 to qualify chip selects seems to be lamentably common in 6502 hobby systems, and is incorrect design practice.

Wait... people attach the clock (Ø2) to chip select inputs? I must be misunderstanding what "qualification" means.

Why don't people simply just attached the chip select input to the output of the address decoding circuitry to access that chip? Actually, come to think of it, as an example, I seem to recall that EPROM chips such as the 2764 have both an output enable and chip select- they accomplish different things, but couldn't they both be attached to the output of an address decoder? It's been awhile since I've looked at a schematic that required me to worry about these things .

Of course I'm simplifying a bit- the address decoder would need to be combined with the '816s VDA/VPA to determine whether to actually access CE.

[GARTHWILSON]

Quote:

Wait... people attach the clock (Ø2) to chip select inputs? I must be misunderstanding what "qualification" means.

Not directly of course.

For some I/O ICs however, phase 2 will need to be brought into one of the inputs of the chip-select logic (not the IC itself), if not also to the write-enable logic and/or the output-enable logic. It may be for example that the IC should only be selected if there's a specific combination of address-line states along with phase-2 high, and not otherwise.

ICs like the 65c22 have R/W\ and phase-2 inputs, and phase 2 must not be brought into the chip-select logic for these ICs, as their chip selects need to go true before phase 2 rises.

Quote:

I seem to recall that EPROM chips such as the 2764 have both an output enable and chip select- they accomplish different things, but couldn't they both be attached to the output of an address decoder?

You can do it with a 6502 (in fact that's what I've been doing for 25 years), but don't do that with an '816, because it would have the EPROM trying to drive the bus with the output data byte during the phase-2-low time when the processor is trying to drive the same bus with the bank byte. It would be best to select the EPROM when the address matches (to give the EPROM an early start in fetching the data), but not enable its output until phase 2 goes up.

[BigDumbDinosaur]

GARTHWILSON wrote:

For some I/O ICs however, phase 2 will need to be brought into one of the inputs of the chip-select logic (not the IC itself), if not also to the write-enable logic and/or the output-enable logic. It may be for example that the IC should only be selected if there's a specific combination of address-line states along with phase-2 high, and not otherwise.

Possibly the case with the 65C02, but not with the 65C816, which can tell the chip select logic when a valid address is present.

Quote:

ICs like the 65c22 have R/W\ and phase-2 inputs, and phase 2 must not be brought into the chip-select logic for these ICs, as their chip selects need to go true before phase 2 rises.

As I emphasized a few posts ago:

• "RWB should be directly connected to RWB on the microprocessor, Ø2 on the device should be directly connected to Ø2 on the microprocessor, and the glue logic that selects the device must do so without qualification by Ø2."

Quote:

Quote:

I seem to recall that EPROM chips such as the 2764 have both an output enable and chip select- they accomplish different things, but couldn't they both be attached to the output of an address decoder?

You can do it with a 6502 (in fact that's what I've been doing for 25 years), but don't do that with an '816, because it would have the EPROM trying to drive the bus with the output data byte during the phase-2-low time when the processor is trying to drive the same bus with the bank byte. It would be best to select the EPROM when the address matches (to give the EPROM an early start in fetching the data), but not enable its output until phase 2 goes up.

As should be done with all devices. RAM and I/O silicon should also have its /WE (write-enable) qualified by Ø2 to avoid the possibility of a wild write and data or register content corruption. Again, none of this applies to the 65C21, 65C22 and 65C51, whose control lines (RWB, etc.) should be directly attached to their counterparts on the MPU.

[BigDumbDinosaur]

cr1901 wrote:

I must be misunderstanding what "qualification" means.

Probably not. However, for the sake of clarity and in the context of our discussion, "qualification" means that an /OE (output enable) or /WE (write enable) control input on a device is not to be asserted unless Ø2 is high. The data bus should be considered to be invalid during Ø2 low on the 65C02. During Ø2 low, the 65C816 emits the bank address on the data bus.

Enabling /OE during Ø2 low in a 65C02 system is probably harmless (although the addressed device's timing may be violated), but will cause data bus contention in a 65C816 system. Said contention, in addition to possibly producing significant transients, may result in an improper effective memory address being generated if the bank address is being latched, as a undefined bit pattern may be present on D0-D7 at the time when the latch is closed (on the rise of Ø2).

Enabling /WE during Ø2 low may violate timing on some devices and in the case of the 65C816, may cause the device to accept the bank address as valid data. If the addressed device is I/O hardware, the acceptance of the bank address as data may cause the device to behave in an undefined or unexpected manner, e.g., the occurrence of an unintentional change to the device's configuration.

I will reiterate that the above scenarios don't apply the W65C21, W65C22 and W65C51. These devices "understand" the 65C02/65C816 bus protocol and should not be subjected to Ø2 qualification of any kind.

[LIV2]

Thanks again, after reading the thread on high speed digital design and I don't think I'm going to get near 10Mhz anyway.

The reason for that is that my design will use ISA style connectors for peripherals connected to the cpu bus, and as I understand it'll be too noisy to get above a few mhz, not really an issue though since I'm just doing this for fun and probably won't be able to tax the system enough to need that much speed, at least for a while.