Hi there MichaelM!
Thanks very much for looking!
MichaelM wrote:
With the caveats out of the way, I suspect some of your problem may stem from the breadboard. However, if your schematics are up to date and accurate, then there are number of logic errors that mean you don't have a working board with breadboard induced reliability issues.
The schematic is mostly up to date, though the symbols used are of variable quality. Some I found online, some I cobbled together. I use gEDA, which is pretty good though probably not as good as the big commercial software.
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First, virtually every where that a signal is active low, you have shown a bubble on the pin. However, you do not show the bubble on the nDMA/BREQ pin of the processor.
Yes, the usage of bubbles is a bit "variable", and sloppy. The bars are right though.
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This is an active low pin, and the way your schematic is wired, i.e. it is connected to ground, the processor is not going to execute any instructions and will instead grant the bus to an external bus master. You can check the bus state on the {BA, BS} pins. The data sheet indicates that a {1, 1} state on these pins indicates that the nDMA/BREQ pin is low and that the processor is halted until it is released, i.e. driven or pulled to logic 1.
If you look closely you'll see that nDMA/BREQ is tied high, to vcc. I was a tad sloppy and drew the "pull" upside down, just because that was the easiest way to place things. I'm quite new to this all, and will try to ensure that my "high"s go up and my "lows" go down in future...
A stupid question: what should you do with unused outputs? Is it ok to leave them dangling, or should they be tied low? Or high? I tend to leave them floating. Obviously unused inputs is a different matter, and something I seem to be sloppy on.
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Second, MRDY is a the memory ready signal. You show it connected to signal ground. In this state, the data sheet indicates that the processor will insert wait states. If you don't have logic to drive it, then connect it to logic 1.
My Vcc tie is upside down on this pin.
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Third, you have not connected the nRD input of your PCF8584 component to the nREAD signal that you generated on your processor sheet to output enable the ROM and RAM. This part operates in the same manner as those two components.
I wasn't sure what to do here. The datasheet hints that the nRD pin is used when the PCF8584 is used with a Z80, which (I understand) has separate read and write lines, vs the Motorola-style RnW pin. I will give the sheet another read and certainly give this a go.
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A similar comment regarding the bubbles on the nIACK, and nINT pins of the PCF8584 applies. I recommend terminating all unused pins like nIACK to guarantee behavior. As a nit, you have applied a > on the inside edge of your processor symbol for the E and Q clock outputs. If you want to apply a decorator to these pins it should be a square wave rather than the > symbol which generally signifies an edge sensitive input not a clock or strobe output. Also, from my perspective, the wide bar on the battery is generally taken to be the positive. Please check that the battery pins and polarity are correctly connected to the VBAT pin of your Dallas time keeper.
Regarding the symbols, you are right of course. It just came down to time for the most part, to get the pin numbers and names right.
Oops! The battery, in he circuit, is round the right way. I wasn't sure which way round the symbol should go in the schematic. It seems that long line = long LED lead, a useful mnemonic!
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Finally, I would recommend connecting your unused 7400 gate to BA, BA and its output to an LED. When the LED is on, the processor is halted. This would be a relatively simple health/status monitor for your processor.
Using LEDs on BA and BS sounds like a great idea.
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In summary, it appears that you have a few schematic errors, and those are sufficient to make your design stop executing instructions shortly after reset. In light of these errors, I would stay on the breadboard until the changes I identified above are made and you can demonstrate a short loop with a two channel scope. I use a sequence something like NOP NOP BRA $0 to test that the lower two bits of the address bus is incrementing in a consistent manner.
Thanks very much for the tips and help. I will certainly stay on breadboard until I get some decent reliability out of my design.
Lawrence