During my experiments with the W65C02, I've been looking at the timing, and I noticed that the datasheet seems very conservative compared to the real silicon.

I have been looking especially at the relationship between PHI2 and A0-A15,MLB,R/W,SYNC,VPB (the two waveforms at the top of the timing diagram in Figure 6-3 of the WDC datasheet, see screenshot below).

Now, from the falling edge on PHI2, there's a tAH (Address Hold) time specified for which the A0-A15 and control signals are still valid. This is min. 10 ns. But then the datasheet indicates a second transition on A0-A15 a little bit later. This is specified as tADS (Address Setup), with max time of 40 ns (at 3.3V operation).

It seems strange to have two separate transitions on these signals. I would expect a modern design to have registered outputs clocked by the global clock, that only change once. Perhaps they mean that there's only one transition, which occurs somewhere between tAH and tADS ? Still, why the huge gap ?

In practice, I see only one transition, and it occurs about 10 ns after the falling PHI2 edge. This makes a lot more sense, but of course, since the datasheet doesn't guarantee it, we can't really rely on it.

Has anybody else noticed this ? Any thoughts ?

I see tADS as the constraint which sets up the address for the next clock edge, and which is referenced to the preceding one. It might be clearer to subtract your cycle time, giving a negative number, and placing this address change prior to the clock edge.

I was thinking too that a 'setup' time is typically used to constrain stability of a signal before a clock edge. But since the 6502 is generating this address, I can't make any sense of that interpretation.

The CPU is striving to meet the setup of the address decode and receiving device - that's how I read it.

So, basically what they're saying is that the old address is valid for at least 10 ns after the edge, and the new address is valid no later than 40 ns after the edge. In that case, timing is really sloppy If I'm right in guessing that these signals are registered on the falling phi2 clock, we're only talking about the propagation delays of the output drivers. Maybe the specs are valid for really heavy bus loading (then again, maybe not. Bus loading is specified at 35 pF max)

The reason I'm interested, is because it has a big effect on access time, which is now 70 ns. If it turns out address are valid earlier, the access time increases, allowing for example SDRAM as external memory, with enough time to set up row/column during the 6502 access time.

Bear in mind that sometimes the low bits of the new address have only just been delivered to the data pins by the clock edge - they have to be passed across the chip.

Yes, but if they are registered outputs, it shouldn't matter how far they have to come before the clock edge (assuming I don't exceed maximum clock rate). Looking with my scope at the lower address bits, I can't see any jitter in the timing, even when running the entire test suite, all transitions on the address bus just go right through the same spot.

I seem to remember the path goes through three transparent latches but I can't remember which phases are used. You might well be right that this arrangement affects the cpu's setup constraint, and not the clock-to-q timing.

I'm with you. That does seem to be what the diagram is saying.


I, too, wanted to mention transparent latches. Correct me if I'm wrong, but instead of using edge-triggered flip-flops I thought 65xx series chips operate by using their internal buses as transparent latches, driven "Phase-1, Phase-2" fashion so as to move data from place to place without creating a race condition. IOW, the address lines are not the output of an edge-triggered register, but are just a reproduction of whatever activity appears on an internal bus. If there's "sloppy timing" on the internal bus then that'd be reproduced on the address lines. Am I over-simplifying?

This still leaves the question of why sloppy timing might occur on the internal bus. My first thought is that the timing might vary according to selection of different address sources -- the Stack Pointer, the PC etc. But by running the Test Suite you're invoking all the options, and the 'scope shows no variability in the address lines' transitions. And yet, the people who wrote the timing specifications obviously were worried about variability. Is it plausible that their (apparently unjustified) concern pertains to selection of different sources on the internal bus?

cheers,
Jeff

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My guess at this point is that the silicon has been upgraded. They now have both hard and soft cores in HDL, and it's a tiny design, so it should be fairly easy to move to a new manufacturing process with improved timing. Given the progress in the semiconductor industry, it would be hard to avoid that. And then somebody probably didn't feel like it was worth it to publish new timing diagrams.

As far as the technology, I highly doubt they still use transparent latches. They even have Verilog models for FPGA, and FPGA designers do everything they can to make you use flip flops instead.