Since I finally found a little time, I went back to work on my project. I've got a few schematics of a single board computer. But the expandability bus is in the back of my head.

So I contacted Herb Johnson who is just about the only person to list STD Bus backplanes for sale for under the 300$ for a new Vector STD backplane.

Anyways, I got to thinking, and the reason I did not post it on my other thread is because I wanted this topic to be more about the bus itself, and how to implement it. As a guide to others who may decide to use the same bus in the future.

So I am looking at the 56 pins of the STD bus.

• 1-6 & 53-56 are power lines.
• 7-14 are the data (D0-D7) lines.
• 15-30 are the address lines.
• 31 is a write request line.
• 32 is a read request line.
• 33 is a I/O address select line.
• 34 is a Memory Address Select line.
• 35 is a Write expansion line.
• 36 is a Memory Expansion line.
• 37 & 44 are Interrupt Request lines.
• 38 is the CPU cycle sync line.
• 39-40 are CPU status lines.
• 41 is a Bus Acknowledge line.
• 42 is a Bus Request line.
• 43 is a Interrupt Acknowledge line.
• 45 is a Wait Request line.
• 46 is Non-Maskable Interrupt line.
• 47-48 are System Resets.
• 49 is the Processor Clock.
• 50 is AUX timing.
• 51 is Priority Chain Out line.
• 52 is Priority Chain In line.

So I had a few questions, never really doing any microcomputer stuff and I am a little confused. Mainly on one question so I'll ask that first.

How does the processor card create addresses for each card?

Dimitri

I was wondering what in the world you were doing, then realized you were lumping all the various power and ground lines together in the first line, to shorten the list I guess.

I could copy and send you the manuals for a family of 6502 STD-bus CPU boards and some other boards if you like, and that should clarify things. I don't think I want to try to take the time to scan them all and reduce them to get a decent file size. If you're agreeable, you can PM me a snail-mail address.

I can't believe Wikipedia doesn't have an STD bus entry! They mention STD-80 in another article and said it has 80 contacts, which is incorrect. (It has 56.) It was a very long-lived, simple (hence the name, "Simple To Design", or STD), rugged, popular, industrial bus, at a fraction of the cost of VME. At its peak there were over 100 manufacturers of STD-bus equipment. As 16- and 32-bit processors began to take over, STD-32 came along which is a backward-compatible bus, with the board-edge contacts arranged so an STD-80 card's contacts would still line up in the right places and the additional ones in the sockets didn't contact anything on the board. STD-80 and STD-32 boards could be mixed on the same backplane.

The bus had greater use back when everything took more room. For example, you could have a separate memory board for a few MB of memory. Now you can get that much and more in a single socket, or a GB or more in a module, so the CPU board doesn't have to go out on the slow backplane to access it. You might have a hard disc on another card, whereas today you could put a small flash chip or SD module on the processor board and not have to go out on the backplane to access it. You get the idea. As more and more fit on the SBC, the need for the backplane decreased-- or at least the number of required slots did. I built and programmed a couple of automated test equipment (ATE) setups about 20 years ago, and although it worked out well at the time, I would probably not need the STD bus today.

http://www.controlled.com/std/faq.html seems to give a fair introduction to STD bus. Win Systems is one of the major STD-bus manufacturers today. This page starts with a .pdf file called "STD bus: Performance Without Complexity". Actually, although Win Systems doesn't have any 6502 STD SBCs, what you find there might give all the explaining you need (and you'll get it faster than I'll get anything sent to you).

My goal is to fit the entire "computer" on the single STD card. So it can be removed from the system and be used as a single board computer without the rack.

The reason I decided to try my luck using the STD system, is cause since you mentioned it, its fascinated me to the point I think about it just as much as my project! And because I can't leave well enough alone, and over time it would allow me to increase the use of the computer, similar to PCI or PCI-X cards currently in modern computers. The entire SB"C" itself would be on the one card to limit off the board requests.

PS. The Wiki entry for the S-100 bus with the error has been corrected

Dimitri

You might want to look into the STEbus standard as well. With only 64 pins to connect (out of a 96-pin connector), it seems like it'd be easier to get working and/or to debug.

Although, I've not found any timing diagrams for STEbus online, so considering its origins, I assume that they're essentially identical to VMEbus.

If you want/need a simple 6502-based bus system, I have designed one for my selfbuilt computer http://www.6502.org/users/andre/csa/index.html and use it since 1989 actually, with a number of available board schematics (although hobbyist quality only)

André

Another thought/suggestion here - if all you're needing off-board is occasional access to non-(time)-critical I/O hardware, especially if the driver is either soft-loaded or fitted as [...]ROM on the SBC itself, then you might want to consider something similar to Acorn's "1MHz Bus".

A quick outline: A pair of 256-byte pages (normally $FCxx and $FDxx on Acorn's 8-bit machines) are mapped out to a 34-pin connector; 8 pins for data bus, 8 for address bus, 10 marked as "0V" (crosstalk elimination), and 8 for select, interrupt, timing and an input into the audio circuitry.

And, of course, if you're running the CPU at several MHz, clock-stretching and/or clock-switching (between "normal" and 1MHz cycles) can be used when the relevant address-space is addressed.

HTH,

--Martin

_________________
Martin Penny

.sig in beta - full release to follow.

Thank you both for the replys. I am reading the STEbus information on the internet as I type this.

I also looked at your projects, keep up the good work Andre.

Martin, Actually at first I thought of a non-specific bus just using the STD form factor for the cards, to route SPI, I2C, 8-bit non-serial data etc. But if I am going to put that much work into it I figured I could make a useable bus, and perhaps even interface commercial products to it, making my cards work both as a SB"C" but also as I/O cards for current systems.

PS. I apparently came into possession of not one, but 3 6801 CPU's according to the internet, from a Coleco Adam PC. Funny how it has 3 of them, and a single Z80 CPU to run itself.

Dimitri

This is not a direct answer, but I looked at my code for the ATE, and I see the I/O base address was set up on the SBC to be $4000. The STD bus base address (in the I/O space) was $4200. I had two signal generators on the bus, one with base address $4250 and one with base address $4260. An A/D and D/A card's base address was $4200 (same as the STD-bus base address). The base address of a memory board was $4280. From there, you can imagine the address decoding on the SBC. The cards had jumpers so you could set them up to avoid conflicts. Several other cards had the STD-bus form factor, but were not on the actual bus, and were fed serially with chains of dumb shift registers. The SBC's I/O ICs' base addresses were: 6522 VIA at $4800, 6551 ACIA at $4A00, 6532 RIOT at $4400, and 6520 PIA at $4C00.

I had some minor problems today that kept me from copying the manuals for you, so hopefully tomorrow.

Actually Garth, that makes a lot of sense, and answered my question enough to keep my idea going.

So far I am thinking a ATmega640/1280/2560 chip will have enough I/O ports to interface to the bus, from there, it will act as a transfer system from the primary components on the board, be it I/O expansion or my SB"C" to the backplane. Interface to the rest of the system will be through the optional UART, SPI or TWI (I2C) so there will be plenty of options on how to design the rest of the board (maybe even a parallel port if there is enough I/O ports). Maybe I'll include a DIP switch to allow the selection of the address range acceptable for the device.

Effectively, the ATmega STD bus chip, a ATxmega chip, a SDRAM chip and the required hardware will be in the lower side of the card rest will be a prototyping area with the top portion dedicated to a header area. The ATxmega will be my SB"C" processor while the SDRAM is for more memory capacity for it. Only the ATmega chip is needed for the STD interface so I will include holes for transferring the routes for access to the prototyping area so a ATxmega is not needed.

Reason being is if I have these boards made to accept the SMT microcontrollers, the price gets high, so it would be cheaper to made a few "standard" cards with prototyping areas then to make single boards.

Take your time Garth I appreciate it! Since your including 6502 STD drawings, I will get around to and interfacing one with this project of mine.

Dimitri

Designing the board for the interface to the STD bus, I had realized I screwed up.

Due to the way the pins are layed out on the STD bus, I had a heck of a time to route the lines to the data pins, till I realized that they were meant to be used with DIP through hole parts, which made lay out alot easier.

I also after looking at various STD boards from PDFs added 74LS245's and 74LS244's to the pins, not sure if they are really needed with the AVR's but figure due to the length of some of the backplanes that they can't hurt. Also simplified the layout of the circuit boards as the AVR I was going to use as the bus master was a SMD and I need through holes as I described above.

Also purchased a book, "STD Bus Interfacing" by Titus from Ebay, as it had the best condition copy of it, which describes the bus in detail. So I will have a future reference.

Dimitri