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agsb
 Post subject: A new toy memory map
PostPosted: Wed Nov 20, 2024 8:30 pm 
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Joined: Mon Jan 09, 2023 9:33 pm
Posts: 29
Hello,

I'm learning how to make a 65C02 SBC toy, and ask all about if those circuits are correct.

Any suggestions or corrections, are welcome.

Planning use,

1 x 1.8543 Mhz

1 x W65C02
2 x W65C22
1 x NM6551

2 x HM62256
1 x AT28C64

1 x 74HC10
1 x 74HC00
1 x 74HC138

Thanks all,

PS. I repost this at SBC topics


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GARTHWILSON
 Post subject: Re: A new toy memory map
PostPosted: Wed Nov 20, 2024 9:37 pm 
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Joined: Fri Aug 30, 2002 1:09 am
Posts: 8543
Location: Southern California
agsb wrote:
PS. I repost this at SBC topics

Please don't, as it adds needless clutter to the forum.  I think everyone here already checks the entire forum regularly except perhaps the BASIC or Forth sections if they're not interested in those.  Also, when you have more development on the same project and topic, please keep it together, even if you think it's old.  A lot of people think they have to start a new thread about the same thing just because the one is old; but it's better to keep going on the original one, for these reasons:

  • to keep the related stuff together,
  • to avoid repeating information (particularly in the replies), and also
  • to avoid cluttering the forum with duplicate topics; and
  • if the same one is continued, those who have posted there get an email notification of replies (when notifications work).

Thanks.

Garth  (moderator)

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BigDumbDinosaur
 Post subject: Re: A new toy memory map
PostPosted: Thu Nov 21, 2024 12:08 am 
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Joined: Thu May 28, 2009 9:46 pm
Posts: 8503
Location: Midwestern USA
GARTHWILSON wrote:
agsb wrote:
PS. I repost this at SBC topics

Please don't, as it adds needless clutter to the forum...

Also, please don’t post schematics in color.  :D

As for your circuit, what is the purpose of the ENABLE input to the read/write logic?  If it is low during a write cycle, /WR will stay high, producing write-protection for something.  However, I don’t see anything that would need write-protection.

The memory map you are planning is not possible with your current design.  You are indicating that “devices” will be mapped into the range $E000-E0FF in 16-byte segments. You will need a lot more address bus decoding to achieve that than you have now.  I suggest you rethink your memory map and look at using a 74xx138 3-8 decoder to select your I/O devices.

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agsb
 Post subject: Re: A new toy memory map
PostPosted: Thu Nov 21, 2024 5:43 am 
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Joined: Mon Jan 09, 2023 9:33 pm
Posts: 29
Thanks. Garth  (moderator)[/color][/quote]

I know, I had already posted here when I noticed that there was a topic about SBC, I tried to delete it here and just leave it there, but I couldn't.
Which of the two should I delete (how)?
Sorry, I had already posted it when I remembered the colors, I'll put it back in black and white.
Thank you for your attention and patience.
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agsb
 Post subject: Re: A new toy memory map
PostPosted: Thu Nov 21, 2024 5:48 am 
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Joined: Mon Jan 09, 2023 9:33 pm
Posts: 29
The ENABLE signal is for suspend both RD and WR, if need, or just tied to VDD 5V.

Quote:
[color] I suggest you rethink your memory map and look at using a 74xx138 3-8 decoder to select your I/O devices. [/color]


Yes, exact what I plan to do.
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