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fachat
PostPosted: Sat May 25, 2024 11:57 am 
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Location: near Heidelberg, Germany
During a recent build I found that my 65816 was not starting up. I found that it seems to be caused by /IRQ low during the startup process. Is that a known problem?

Here's what my system does:
- Phi2 is held low
- /RES goes high
- (system fills boot memory from SPI flash)
- Phi2 starts clocking with the first transition low to high
- normally, the CPU pulls VPB, gets the reset vector and starts

However, if, during that whole time, /IRQ is low, the CPU never pulls VPB and never starts.

Is that a known behavior?

André

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BigDumbDinosaur
PostPosted: Sat May 25, 2024 5:44 pm 
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Joined: Thu May 28, 2009 9:46 pm
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Location: Midwestern USA
fachat wrote:
During a recent build I found that my 65816 was not starting up. I found that it seems to be caused by /IRQ low during the startup process. Is that a known problem?

Here's what my system does:
- Phi2 is held low
- /RES goes high
- (system fills boot memory from SPI flash)
- Phi2 starts clocking with the first transition low to high
- normally, the CPU pulls VPB, gets the reset vector and starts

However, if, during that whole time, /IRQ is low, the CPU never pulls VPB and never starts.

Is that a known behavior?

André

I think the problem is you are letting reset go high with the clock stopped—the state of IRQB is irrelevant.  The 816 requires that the clock be running and stable before the release of reset.  On page 15 of the data sheet, it says:

Quote:
The RESB signal must be held low for at least two clock cycles after VDD reaches operating voltage.

I have experimented with this in the past and have confirmed that the 816 will not reliably start if the clock isn’t stable when reset goes high.

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fachat
PostPosted: Sat May 25, 2024 7:53 pm 
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Joined: Tue Jul 05, 2005 7:08 pm
Posts: 1007
Location: near Heidelberg, Germany
BigDumbDinosaur wrote:
fachat wrote:
Is that a known behavior?

André

I think the problem is you are letting reset go high with the clock stopped—the state of IRQB is irrelevant.  The 816 requires that the clock be running and stable before the release of reset.  On page 15 of the data sheet, it says:

Quote:
The RESB signal must be held low for at least two clock cycles after VDD reaches operating voltage.

I have experimented with this in the past and have confirmed that the 816 will not reliably start if the clock isn’t stable when reset goes high.


Interesting. VDD is stable long before /RES goes high. Also, phi2 is stable - although stopped at low phase...
Does it say it must be running?

And the only difference I saw that prevented the CPU from starting was /IRQ being low.

André

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BigDumbDinosaur
PostPosted: Sat May 25, 2024 8:48 pm 
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fachat wrote:
Interesting. VDD is stable long before /RES goes high. Also, phi2 is stable - although stopped at low phase...
Does it say it must be running?

Let me repeat part of the data sheet’s comment, but with some added emphasis:  :D

    The RESB signal must be held low for at least two clock cycles...

In other words, the clock must be running before reset goes high, with a minimum of two full clock cycles occurring while RESB is low.  Furthermore, the 816 will not start execution until after the completion of six full clock cycles following the release of reset.  It will be evident that execution has started when VPB is driven low as the reset vector is being fetched.

Quote:
And the only difference I saw that prevented the CPU from starting was /IRQ being low.

The state of IRQB will be irrelevant when reset goes high, as one of the steps taken during the reset sequence is to set the i bit in SR, which, of course, disables the 816’s response to IRQs.  The state of NMIB will be irrelevant as well, since that input is edge-sensitive.

This seems to be a case in which it would be better to drive RDY low to pause the 816 than by stopping the clock.  Incidentally, if the clock is stopped while low, the 816 will be emitting the bank bits on D0-D7.

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