If using an FPGA it is probably best to put the whole ‘816 core in the FPGA. It will fit into a small FPGA these days. I am not sure one can get 10 ns pin to pin timing with logic and routing using an FPGA.

I have been thinking of updating the ‘816 FPGA based core to support a better bus architecture. Some of the issues required to support a multi-tasking operating system could be “fixed”. Allocating memory in 64k bank chunks works for me. More than 16MB could be supported by an FPGA version. I enjoy reading about the POC systems.

With a fast ‘816 core in an FPGA cache RAM needs to be used. Doing I/O through an external bus is very slow, which leads to placing the entire SoC on the FPGA.
The SoC bus I am currently using runs at 40MHz+ in the FPGA.

A FPGA based solution could just use a stock FPGA board, which may not be as much fun as having a fixed '816 core to play with.

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