barnacle wrote:
Is there a cycle by cycle guide to the reset sequence of the wdc65c02? The datasheet merely indicates that the reset pin must be held low (active) for at least two clock cycles after the clock is stable, and that there is a reset sequence lasting seven clocks.
Is it a fair assumption that on the eighth clock the processor is about to execute an instruction read?
Neil
It's just as
gfoot described. Here's what I've used for WDC and Rockwell 65C02 devices. Note that the
uPull() function waits 500-nS, takes the CLK pin lo, waits another 500-nS, then takes the CLK pin hi.
The eighth clock cycle is an instruction 'fetch' from the address that you 'pushed' to the 6502 during clocks 6 & 7.
Code:
/******************************************************************************
* core 'blind interface' functions *
* */
void uReset() // ****************************************
{ clk(1); // clock = 1 *
res(0); // reset = 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~ *
_delay_us(100); // *
uPull(ram); // (1) *
uPull(ram); // (2) *
res(1); // reset = 1 ~~~~~~~~~~~~~~~~~~~~~~~~~~ *
uPull(ram); // (1) *
uPull(ram); // (2) *
uPull(ram); // (3) *
uPull(ram); // (4) *
uPull(ram); // (5) *
uPush(lo(0xF000)); // address $FFFC (reset vector lo) (6) *
uPush(hi(0xF000)); // address $FFFD (reset vector hi) (7) *
} // ****************************************
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