I don't know if I'm reading datasheets correctly and I don't know if this is generally known but the Western Design Center's W65C265 PIB [Peripheral Interface Bus], described as ominous, has four bi-directional 8 bit ports with striking similarity to Acorn's Tube Interface. There are a large number of quixotic devices which work at either end of a Tube interface and I understand that the Tube protocol works over three or more physical layers. The majority of Tube systems use vintage Acorn hardware at one end or the other and peripheral typically contains four pairs of bi-directional FIFO within a custom chip. (Does this chip use the same manufacturing process as the 4000 gate Ferranti chip used in the Acorn Electron ULA and/or VIPER?)

It is possible for an implementation to use vectored interrupts rather than FIFO (although the extended interrupt system, shipping in the W65C265, was deemed unfavorable when it was proposed in the 65VM02). Indeed, a vectored interrupt system may be superior for this task because it allows function as host or peripheral in addition to permitting deeper buffers. Anyhow, I would like to check that a W65C265 has an electrically compatible parallel interface which works with vintage Acorn hardware, 6809, Z80, 32016, ARMv1-8 and numerous ridiculous simulators in addition to another instance of itself.

I also note that a W65C265 makes a fair approximation of an Acorn BBC Master memory map. Specifically, the internal 32KB RAM may selectively overlay another bank of memory. It is also possible to implement banked RAM/ROM at $8000-$BFFF (or higher). The major difference is that the I/O is on page $DF rather than the traditional $FC, $FD and $FE. However, if a person is inclined to use Tube protocol and OS legal applications, the location of the I/O hole should be fairly immaterial. And for the 65816 fans, a W65C265 also provides this additional functionality, including a blank memory map from $010000 upwards.

It is possible to access a W65C265 via its four serial ports, although these are without hardware handshake and clock rates are tied. Alternatively, the W65C265 microcontroller has sufficient pins to directly connect a keyboard matrix and it is trivial to interface a video display, such as 6845 on opposite clock cycles or TMS9918 (NTSC composite) or TMS9929 (PAL composite) with its own memory bank. It is possible to start with W65C265SXB evaluation board and a bespoke board with all functionality would probably cost less USD100. If I am correct, such a system would already work with an extensive ecosystem of software a peripherals.

Have I missed something or everyone else missed something?

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Modules | Processors | Boards | Boxes | Beep, Beep! I'm a sheep!

Unfortunately the PIB is unusable on the '265SXB board as some pins on port 4 and 5 are otherwise allocated. If the PIB were exposed it would mesh easily I think to an Apple II/IIGS expansion slot as another example.

Also I believe the PIB could be delegated as a priority interrupt decoder. The low address bits fall right on IRQB and NMIB if one were to use the VPB pin of a 65c02 or 65c816 as chip select.

Cheers,
Andy

A single bidirectional byte channel is enough for the Tube, although it's not quite as efficient as Acorn's original chip, as the physical channel has to multiplex the four logical channels. But it's been done, over UART and over a pair of VIAs. So it might be that the 265 could support that.