Hello there, I'm in need of 65xx gurus...
I've tried to build a "plug&play" 40-pin W65C816S module for my Oric (the Oric is a 6502 home-computer from Tangerine), but unfortunately it doesn't seem to work, I guess I have some timing problems...
I started by comparing the pinouts of the old NMos 6502 and of the W65C816S, and it appeared the two biggest concerns were the multiplexed Bank/Data lines, and the clock signals.
On the Oric, the clock is built by a ULA (Uncommited Logic Array) : the 6502 is thus fed with a 1 MHz signal, but this clock has a 2/3 low period and a 1/3 high period (this allows the ULA to make two memory accesses during the low "half-period", and let the processor have one memory access during the high half-period). So I sent the clock (Phi0 input on the 6502 socket) through two LS04 inverters in order to build Phi2 for the whole system, and through a third one in order to build Phi1 (Phi1 is marginally used on the Oric, it only drives a GI AY-3-8912 PSG).
Is this acceptable ? I mean, the NMos 6502 builds non-overlapping Phi1 and Phi2 signals from the Phi0 input, and I am only deriving Phi2 from a slightly delayed Phi0...
Also, I attached a 74LS245 to the Bank/Data bus of the W65C816S. I wired it to side B, and connected side A to the 6502 socket, so that I could drive DIR with R/W. /OE is driven by an inverted Phi2.
I have absolutely no idea whether this is correct or not (on a timing issue)... Does this additional inverter introduce a nasty delay ?
In one word, what shall I do ?
TIA,
Fabrice
PS: Hello Mike
PS2: There are schematics of the Oric on
http://oric.free.fr/hardware.html