My core uses only positive edge clocks, with 1 clock per 6502 cycle. It leaves almost a full cycle for memory access, since the address and control lines are valid at the clock edge, and not delayed. But like you said, the consequence is that it's not identical to a real 6502 with respect to bus cycle timing.

I'm sure that a cycle-accurate 6502 model using only one clock edge is perfectly possible, if indeed we don't already have one somewhere. (Arlet, yours is special because of the use of synchronous memory, I think.)

It's true that the NMOS 6502 is a two-phase design, and it's true that the Z80's approach is to use multiple cycles (T-states) for access. (The Z80 has an easier time of driving the strobes of a DRAM as a consequence.)

It's also true that designs using the 6502 commonly use phi2 as a kind of strobe, to have a mid-cycle demarcation. But as Arlet's figures show, even the CMOS version of the CPU doesn't have any external behaviour which relates to the rising edge of phi2. Only the falling edge.

And, it's also true that several designs using the 6502 make use of the fact that RAM access times are somewhat shorter than a half-cycle, to allow for two RAM accesses within one clock cycle, where the second RAM access is for video (or maybe other things?) This is clever, but it amounts to double-clocking the RAM, not as evidence that the 6502 is double-clocked.

As an interesting illustration of other approaches, see the Oric:


(I was once in a death-march CPU project with a target of 30MHz, which was struggling to meet 10MHz, and was asked by a senior manager whether our 4-phase clocking would allow for a marketing position as a 40MHz part (or maybe one day as a 120MHz part.) Being the kind of engineer I am, I was very direct in saying that it wouldn't. Probably career-limiting, but that's me!)

What I mean by this (in the nicest possible way) is that it's a misuse of terminology to say it's two CPU clocks for a memory access. The NMOS 6502 is certainly a two-phase design, but any other implementation need not be, even an indistinguishable one.

Michael: thanks for your analysis. Note that the transistor count from the visual6502, which has I think made its way into Wikipedia, is only a count of pull-downs. So an inverter is only a single transistor, and an N-input gate is only N. The NMOS 6502 was found to use transparent latches extensively: they cost only two transistors. But the net effect (as you imply) of a pair of transparent latches clocked on opposite phases is an edge-triggered flip-flop. As I say above, we can model all the behaviour of a 6502 using edge-triggered flops. What you find is that the address bus cannot be driven directly from a flop, but must be driven via a mux. This, together with the need to get from the data bus capture flops across to the address bus pins, is the reason that the address bus becomes valid a bit later than you'd like.

Cheers
Ed

One problem I see with a single clock/single edge implementation of a 6502 is the back to back write cycles. You get these for instance in a JSR call, where the PC is written as two bytes in two consecutive cycles. If you don't qualify the write enable signal with the PHI2 clock, the write enable will be asserted for two cycles, while address lines are switching between the first and second cycle. Worse, they won't be registered, so they'll have glitches and will be skewed with respect to each other.

But this is how the real 6502 operates - with an asynchronous memory, and generally with the write enable qualified externally with phi2. (Any other suitably-timed gating signal would work - phi2 is convenient rather than crucial.)

Your approach certainly has merits, but it doesn't constrain a cycle-accurate implementation. In order to convincingly make the point about cycle counts and the unimportance of the rising edge of phi2 in the external behaviour of the commercial 6502s, we need not take into account any other implementations which have other goals.

Cheers
Ed

Sure, you can output an inverted clock as the PHI2 output, but you also need the timing constraints to make sure the address/data lines are stable before the negative edge of the clock (positive edge of PHI2). In effect, you're back to working with both edges, at least for part of the design.

Sure - but I feel you're talking about how to make a convenient-to-use core, and how to use it. That's fine. I was trying to explain why it's wrong to think of the 6502's memory accesses as taking two cycles, or to think of the 6502 as needing two operations internally which correspond to two cycles.
Cheers
Ed

I was disagreeing with your statement that you can build a cycle-accurate 6502 model with only one clock edge, since at the very least you need to generate the PHI2 signal, and use it in timing constraints. Of course, you can cheat by generating the PHI2 externally, and cheat even worse by ignoring the timing constraints.

Are you saying there are timing constraints to the rising edge of phi2? One way of restating my position is that an FPGA 6502 need have no tight constraint on the duty cycle of the clock.

There are timing constrains between the address/data out bits, and the rising edge of phi2. The edge on phi2 will be used to trigger the actual write, so that means that the address and data must be stable before that. In order words, you need to tell the FPGA tools that the address/data out bits only have half a clock cycle (minus setup/hold) to be valid.

Hmm, I see that such a constraint would be adequate, but not true to the 6502: I'd say outputs should be valid shortly after the falling edge of phi2. In practice it amounts to the same thing, but for my present pedantic purposes it suits me better!
Cheers
Ed

While I still believe that a straight cycle comparison between a Z80 and a 6502 is not valid, the quality of this discussion is amazing!

Arlet, I think you put the nail in the coffin for me - the back-to-back writes really point out the 2 sync points per cycle issue even more than my goofy examples.

I think that the way the 6502 is constructed just does not map to our synchronous logic easily. I will make one more plea for my case.

Consider a CPU that does this:

always (@posedge clk) begin
AB <= PC;
PC <=PC+1;
end

always (@posedge clk)
DATA <= DB;

Every clock we are one data element behind.

If we flop in the data on negedge instead, we can do a full access every cycle:

always (@negedge clk)
DATA <=DB;


This almost fits the timing model. I would not feel right about saying that this circuit runs at 1MHz and comparing it to a Z80 running at 1MHz - at least without making a note that I am cheating a bit (and I love cheating!).

Now I am not saying that's how the 6502 does it. All I am saying is that if CPU A can do a full memory access inside one cycle and CPU B is synchronous, you are comparing apples and oranges. Very clever apples. Wonderful apples designed by brilliant engineers to whom I will feel forever in debt. But not oranges.

_________________
In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Enso:

There are times when you want to apply an address to a RAM before the next valid edge of the clock, and then hold the value. This requirement is perfectly satisfied by a latch. Recent experience with the Xilinx ISE synthesizer/simulator prevented my use of such a device inside the FPGA on another project; neither tool like the explicitly defined latch even though it is a support capability of the CLB/IOB bi-stable elements.

An alternative implementation to your interface model may be:

In this alternative implementation, the next value of the PC is computed while the current value of the PC is driven out. At the falling edge of the clock, the transition from phase 1 to phase 2, the current value of the PC is registered into the output address register, rAO, and the pseudo-latch multiplexer is switched to point to the registered value of the output address; this action sustains the current cycle's address until the next phase 1, i.e. the rising edge of the clock.

The point is to show that data bus actions occur on the rising edge of the clock, and PC actions take place on the falling edge of the clock. There is a skew of half a cycle between these two domains, and only when there is a transfer from one to the other will there be a need to carefully monitor the delays. In an FPGA, the transfer between these two domains requires that the path delay from the output of the ALU to the address output register be less than half a clock cycle.

In the case of the 6502/65C02, a series pass gate reduces the path delays and simply introduces an incremental delay through the output address latch. Since a true latch is used to hold the output address, the constraint is that the phase 1 latch enables do not overlap with the latch enables of phase 2. Further, from the perspective of the memory, the incremental path delay from the ALU to the address output must be subtracted from the address access time of the device in order to guarantee that the output data is valid when the phase 2 latch enable captures the data into the data input register.

The dead zones between the two phases' latch enables should account for the path delays within the part. Simply raising the threshold on the clock signal comparator is sufficient to create non-overlapped phase 1 and phase 2 latch enables in the part. In most FPGAs, we don't have that kind of control within the clock generation and distribution network. The closest we can come to the 6502's clocking technique is to use the multiphase outputs of the DLLs/PLLs.

_________________
Michael A.

This has been extremely stimulating. Please understand that I never said that the 6502 is doubleclocked. Only that a 6502 cycle is more than a Z80 T-State, and the comparison is not simple.

Who cares, anyway. I am very happy about the 6502's cleverness. Using 2MHz RAM half the time encouraged some amazing designs that use the free cycles for video access without slowing down the processor. And being clever should not be a disadvantage, ever.

I wish engineering schools would look closely at classic design like the 6502, Wozniak's Apple 2, TV Typewriter etc. Clever engineering (and everything clever) is becoming a lost art.

_________________
In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Ah, well that's very easy to agree with!
Cheers
Ed

BTW, at least one university course is using visual6502 for teaching purposes.

Michael: thanks for your note about the PDP-6. There's a lot of good stuff in Gordon Bell's pages, including a pdf on "The evolution of the DECsystem 10" - which mentions the PDP-6 control system because the PDP-6 was the beginning of the journey to the 10.

Cheers
Ed

(There's another, bigger, more comprehensive pdf "Computer Engineering - A DEC view of hardware systems design" again by Bell and friends.)