JohanFr wrote:
However, the documention for writing to T1L ($06) worries me:
Is it WDC documentation you're using? Not a great choice, IMO... for 65C22, 65C02 and others I much prefer the doc from Rockwell... but even their 65C22 doc is occasionally hard to understand. That's because the chip itself has some subtle (but useful) nuances.
JohanFr wrote:
the documention for writing to T1L ($06) worries me:
"8 bits loaded into T1 low order latches. This operation is no different than a write into the T1 Low Order Register"
T1 Low Order Register? So, we're drawing a contrast between Reg $06 and Reg $04, is that right?
According to my notes (based on Rockwell), Register $04 and Register $06 behave almost identically... and the exception pertains to reads (not writes). A read of Reg 6 won't clear the T1 flag in the IFR, whereas a read of Reg 4
will clear the flag. (Both return the same data. But the designers apparently anticipated a need to be able to peek at the timer without scuttling a nascent interrupt.)
I suspect that the snippet you quoted is some author's garbled re-interpretation of the behavior documented by Rockwell.
Edit: oops, that's probably too harsh. The snippet isn't incorrect. But it's entirely unhelpful unless there's an accompanying snippet that pertains to reads, whose behavior
does differ between Reg 4 and 6.
Edit: On a broader scale (ie, 65C22 aside), when one finds doc confusing, it can often be helpful to find an alternative version of said doc.
-- Jeff
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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html