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PostPosted: Tue Dec 26, 2023 1:50 pm 
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I wrote an emulator for my MicroPET, using Sam Falvo's lib65816. I submitted a merge request for a few small changes even.

What I am now looking for is how to support the 65816 in the emulator's built-in ML monitor. What I stumbled over was the support for the 65816 M/X register width modes that actually change the opcodes significantly depending on internal CPU state that is not known to the ML monitor.

Do other monitors have specific commands to change disassembly mode? If so, which ones? Or there other ways?

I know I could check the emulated CPUs flags, and, in the disassembly check for REP/SEP. I will probably do that but it's not perfect and I may want to jump to some code in another mode directly.

Would something like dxm/dx/dm work as commands to auto-set the mode bits for the disassembly?

Your thoughts?
TiA

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PostPosted: Tue Dec 26, 2023 4:38 pm 
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Sounds like you are trying to do in an ML listing what all assemblers already are doing when assembling. Some assemblers use "mx% 00 - mx% 11" to let the assembler know when using 8-bit or 16-bit registers. I use an assembler that uses only "long/short", which means one has to be really aware when only one of the registers is 16-bit and the other is 8-bit.

I don't know how you would implement "dxm" since an ML listing comes from a hex dump which displays the mnemonics of the instructions. Are you meaning to create 3 new instructions to be a part of the disassembly process?

I wrote a disassembler that just searches for "xce"'s instruction byte and turns 16-bit mode on and off for each encounter. It is not perfect, so I added a second line of defense. I use 2 zero-page locations to indicate when the Acc or X/Y registers are in 16-bit mode. After each page of a listing, if the listing doesn't look right, I just manually set one of the zero-page variables and relist the page of memory.

But 7 out of 10 times, setting the zero-page bytes when "xce" is encountered is more than enough to get it right most of the time.

It changes the way I write programs now. I now group 16-bit subroutines together and the 8-bit ones afterwards so that it reduces the number of times that "xce" doesn't get encountered at the end of a subroutine, so only have to manually set the zero-page variables once, when the 8-bit routines start.


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PostPosted: Tue Dec 26, 2023 4:48 pm 
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My ML monitor on SBC-3 and SBC-4 did not track the register size flags. I used 2 commands for listing the disassembly. "L" gave 8 bit immediate values and "X" gave 16 bit immediate values. It was up to the user to know what mode the section of the source being viewed was in.

When I do finally get to upgrading the Kowalski Simulator with the 65816 simulator, the sim will have to follow the M/X registers in real time when running and will be able to properly display code disassembly.

Daryl

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PostPosted: Tue Dec 26, 2023 6:43 pm 
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First off, a pedantic note.

The 65C816 has two modes: emulation and native.  Register sizes when operating in native mode are not “modes,” as the fundamental behavior of instructions is unaffected by register size, e.g., ROL A left-rotates .A whether m is 1 or 0.  What is affected is the number of bits that get rotated.

In Supermon 816, register sizes during disassembly are tracked by watching for REP and SEP instructions as the disassembly progresses and “decoding” them for changes to the m and x bits.  From this, the disassembler determines how to treat an immediate addressing-mode instruction’s operand.  This process is not ideal, in that changes to m and/or x caused by a PLP instruction can’t be tracked, since such changes are dynamic.  Hence disassembly of the following code:

Code:
         SEP #%00110000
         PHP
         PLA
         AND #%11101111
         PHA
         PLP
         LDX #%1100000000000000

will cause Supermon 816 to think the index registers are set to eight bits, resulting in the LDX instruction’s operand being displayed as #$00, not #$C000.  Similarly, the effect of RTI on the status register can’t be predicted by Supermon 816’s disassembler.

In practice, it hasn’t given me much concern, since when I’m disassembling code during the debugging process, I’m only interested in a short section.  Usually, I’m debugging a function, and since almost all functions condition the m and x bits at entry, disassembly of the function produces the correct results.

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PostPosted: Tue Dec 26, 2023 8:15 pm 
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> …pedantic note…
But in real life most people call them modes, and no-one has ever been misunderstood on this point.


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PostPosted: Tue Dec 26, 2023 9:58 pm 
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BigEd wrote:
> …pedantic note…
But in real life most people call them modes, and no-one has ever been misunderstood on this point.

And your point is...what?

The 816 has two modes: emulation and native.

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PostPosted: Tue Dec 26, 2023 10:16 pm 
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BigDumbDinosaur wrote:
BigEd wrote:
> …pedantic note…
But in real life most people call them modes, and no-one has ever been misunderstood on this point.

And your point is...what?

The 816 has two modes: emulation and native.


I think the point is that you're the only one who makes a point about it. Everyone else just gets on with it.

-Gordon

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PostPosted: Wed Dec 27, 2023 9:58 am 
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I am building an emulator. As such, the trace feature already follows the CPU state and creates the correct listing. Also, I am using xa65 where you can tell the assembler with pseudo opcodes if values are 8 or 16 bit. And it produces the correct listing for it.

Whay I am looking for is when I break out of emulation, and want to examine some code. This could be in the same mode as the CPU is or not. So, I am looking for a way to tell the disassembler how large values are. It seems using multiple commands seems to be the way to go.

Many thanks

PS the same holds true for in-system monitors with disassembly.

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