I ran into something unexpected yesterday when programming a WDC 65C22's T1 for repeated short delays, and wondered whether anybody else had seen it.
I had configured T1 to generate continuous interrupts (ACR = $40) but had not enabled them in the IER - I was just polling the bits in the IFR to see when it expired. The T1 latch value was fairly small, e.g. 20 cycles.
At certain points I'd want to reset T1 to begin its count again in sync with something else, and then later wait for it to expire, like this:
Code:
STZ VIA_T1CH
... other things ...
loop:
BIT VIA_IFR
BVC loop
However, I found at least in some cases that the STZ was not clearing the IFR bit - the loop would seem to exit too soon. I suspected that it could be due to the timer happening to expire at just the same moment that I reset it, but I'm not sure and I didn't specifically try to verify that.
Adding an extra BIT T1CL instruction after the STZ seemed to fix the problem. But it surprised me that this occurred, and I wondered whether it was common knowledge that this extra step was required here.
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