There are some things about the 6522 that I'm sure I'll never be able to recall from memory, and rather than scrolling back and forth in datasheets I decided to collect them all together into a one-page cheat sheet. I thought I'd share it in case it's useful to anyone, or in case anyone already has a better one.

It's not meant to be conclusive documentation, just enough to nudge the memory, reminding which bit is which, or which of the timer register reads and writes have IRQ flag side effects. I've given up trying to actually memorize that!

The diagrams are taken from a PDF of a badly-scanned Rockwell datasheet - but I used these because I liked their compactness compared to the WDC ones. It's good enough for my purposes I think, but also wouldn't be too hard to redraw.

This is great, thanks for sharing!

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BB816 Computer YouTube series

Very handy chart. Thank you.

The 6522 is a fun chip. I used one in a clock/calendar + parallel interface board for an OEM customer some years ago.

Yes, thank you !

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Shaking out the dirty bits!

https://github.com/DonaldMoran

Nice work, George!

I'm attaching two somewhat similar documents which I cobbled together for my own use. Rather than being a general quick reference, they're just some collected notes, comparatively detailed. The first deals with Shift Register operation, and the second lists differences between the "N" and "S" versions of the WDC 6522's.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Nice Jeff. The T2 diagrams there remind me of something that caught me out the other day - I had assumed that when I read or wrote to the SR register to start the transaction, it would immediately load the C2 counter from its 8-bit latch and start counting down from there, so that the first shift would occur T2CL cycles after the SR register was accessed. However, the WDC part at least actually appears to leave T2 counting from whatever 16-bit value it's already set to, and only reset it to the 8-bit latched value each time it expires. This makes some sense regarding complexity, but I don't think it was explicit in either datasheet, and isn't highlighted in the timing diagrams.

It means that if you want the first shift to happen soon then you need to set T2CH to a small value (probably zero) after setting T2CL appropriately. It also means that in addition to the option to change T2CL later in the operation (useful for skipping half a bit, for example), you can also use T2CH to cause a much longer wait before the first shift if you want to.