Hi all;
I was reading through the instruction timing chart (table 6-5) of WDC's W65C02S datasheet (February 2004), as one does, and got a little confused when it comes to the behaviour of the BBRx and BBSx instructions.
It is my understanding that they have only 1 addressing mode which is really a kind of juxtaposition of zeropage and relative addressing (how it's described in Bruce Clark's 65C02 tutorial
here.
Some sources identify this as a bonefide addressing mode, but WDC just call it relative (e.g. c.f. table 6-4).
Looking at the documented bus behaviour of BBRx and BBSx, however, the confusing part is that these sets of of instructions have 2 slightly different entries, one classifed as relative and one classified as zeropage.
The first (relative) goes like this:
Attachment:
File comment: WDC instruction timing chart entry for BBRx and BBSx, classified as Relative
BBSRx_REL.png [ 41.53 KiB | Viewed 589 times ]
Whereas the second (zeropage) goes like this:
Attachment:
File comment: WDC instruction timing chart entry for BBRx and BBSx, classified as ZeroPage
BBSRx_ZP.png [ 42.89 KiB | Viewed 589 times ]
I also note that the first (relative) description adds a note that an additional cycle is taken if the branch is taken, whereas Bruce's document mentioned in the above states that:
Quote:
Unlike other branch instructions, BBR and BBS always take the same number of cycles (five) whether the branch is taken or not
This seems to correspond better with the second (ZP) entry from the WDC datasheet.
So my question is whether there is some distinction in the instruction timing that I am overlooking that warrants these 2 different descriptions or whether it is simply an error in the datasheet.
Thanks in advance.
[Edit: This should have been posted in General Discussions but I cannot figure out how to remedy that so maybe a moderator can move it.]