jeffythedragonslayer wrote:
Sometimes the assembler thinks these are set differently from how they actually turn out to be at runtime, so it generates the wrong size instructions and the CPU gets de-synched from the code, loading operand bytes and trying to interpret them as opcode/admode bytes.
with ca65 you can just directly tell the assembler what width the registers have right now using the .A8 .A16 .I8 .I16 directives.
include those inside your register width switching macros and you shouldn't have this issue anymore. much better than relying on the .SMART directive.
Code:
.macro accu8
SEP #%00100000
.A8
.endmacro
.macro accu16
REP #%00100000
.A16
.endmacro
.macro index8
SEP #%00010000
.I8
.endmacro
.macro index16
REP #%00010000
.I16
.endmacro
.macro all8
SEP #%00110000
.A8
.I8
.endmacro
.macro all16
REP #%00110000
.A16
.I16
.endmacro
also remember to include the .A8 .A16 .I8 .I16 directives at the start of each subroutine, just to be safe.