;**************************************************************************************************
;*                              Command input loop                                                *
;**************************************************************************************************
;*                      This is the Monitor Warm start vector                                     *
;**************************************************************************************************
WARM_MON        LDX     #$FF            ;Initialize Stack pointer
                TXS                     ;Xfer to stack
                RMB7    CMDFLAG         ;Clear bit7 of command flag
                LDA     #$16            ;Get prompt msg
                JSR     PROMPT          ;Send to terminal
;
CMON            JSR     RDCHAR          ;Wait for keystroke (converts to upper-case)
                LDX     #MONTAB-MONCMD-1        ;Get command list count
CMD_LP          CMP     MONCMD,X        ;Compare to command list
                BNE     CMD_DEC         ;Check for next command and loop
                PHA                     ;Save keystroke
                TXA                     ;Xfer Command index to A Reg
                ASL     A               ;Multiply keystroke value by 2 (command offset)
                TAX                     ;Xfer Command offset address to table MONTAB
                PLA                     ;Restore keystroke (some commands send to terminal)
                JSR     DOCMD           ;Call Monitor command processor as a subroutine
                BRA     WARM_MON        ;Command processed, branch / wait for next command
DOCMD           JMP     (MONTAB,X)      ;Execute command from Table
;
CMD_DEC         DEX                     ;Decrement index count
                BPL     CMD_LP          ;If more to check, loop back
                JSR     BEEP            ;Beep for error, not valid command character
                BRA     CMON            ;Branch back and re-enter Monitor
;

;**************************************************************************************************
;
;Interrupt 1 - This is the ISR which is responsible for servicing the IDE controller.
; The RTC does not require any ISR capabilities as no Alarm functions are being used in the BIOS.
; There are extra inserts which can be used if needed at a later date.
; The only functions that might make sense would be to add the Alarm function at a future date.
; Once the IDE controller BIOS has matured, if there's any room left in the allocated ROM area,
; I'll revisit it.
;
;The ISR for the IDE controller will handle the data transfer for LBA read/write/verify functions
; and handle any error functions. By design, the 16-bit Data Transfer feature is used for:
; Reading / Writing / Verifying of all LBA block data and the IDE Identification data.
;
;The BIOS is using the Alternate Status register to determine if DRQ (Data Request) is active.
; This works as a handshake for 16-bit data transfers without issue. Note that the normal Status
; register resets the interrupt when read, so this is only done once in the ISR per loop.
;
;Update: This ISR has been moved to the front of the ISR chain, i.e., this ISR routine gets
; serviced first, then jumps to the next ISR, which services the DUART. This makes a noticeable
; improvement in data transfer from the IDE controller. Note that overhead for this routine will
; add 33 clock cycles if it just exits (IDE controller did not generate an interrupt).
;
;To check if an interrupt has been generated by the IDE controller, the Alternate Status register
; can be read. This contains the same information as the standard Status register but will NOT
; reset the interrupt on the IDE controller. By reading the Alternate Status register first, we
; can first determine what the status of the IDE controller is and take action if required.
; Note that not all bit settings imply an interrupt was generated. Specifically, looking at the
; bit definitions below, Bits 6 and 4 are set when the IDE is ready, hence a normal condition
; where nothing requires any attention. Also, a Busy condition can imply the IDE controller is
; working on a command but may not have generated an interrupt yet. If The Busy bit (7) is set,
; then all other bits are invalid per Seagate documentation, so we trigger on that first.
;
;One annoying feature for IDE is "when" interrupts are generated. For any Read operation, once
; the command has been accepted, data is placed into the IDE buffer, followed by generating
; an interrupt to the system. Once this is done, the system will read the data. By accessing the
; Status register, the interrupt will be reset. This is normal operation. For a write operation,
; The command is sent, then DRQ goes active, which requires the data be sent to the IDE Device.
; Once the data is written, an interrupt is generated after it's completed.
; As a result, there's little function of having an ISR for servicing the write function.
; As interrupts are enabled for the IDE Controller, all generated interrupts must be handled.
;
; Status Register bits as defined as follows:
;       - Bit 7 = Busy (a Command has been accepted)
;       - Bit 6 = Ready (IDE controller is ready to accept a command)
;       - Bit 5 = Write Fault (A write command failed against the media)
;       - Bit 4 = DSC (is set when a Seek is completed)
;       - Bit 3 = Data Request (set when there is data to transfer, read or write)
;       - Bit 2 = Correction (set when a recoverable data error was corrected)
;       - Bit 1 = 0 (not used)
;       - Bit 0 = Error (set when the previous command had an unrecoverable error)
;
;       NOTE: 25 clock cycles to here if DUART ISR is second!
;
INTERUPT1                               ;Interrupt 1 (IDE)
                LDA     IDE_ALT_STATUS  ;Get Alternate Status Register (4)
                BMI     REGEXT01        ;If Busy bit active, just exit (2/3)
;
; - Check for Data Request (DRQ), as the Read LBA operation is the main function
;   of the ISR, which will handle the data transfer from the IDE controller to store the
;   data into memory. This ISR will handle single and multiple block transfers.
;
                LDA     IDE_STATUS      ;Get Status (resets IRQ) (4)
                AND     #%00001000      ;Check for DRQ (2)
                BNE     IDE_READ_BLK    ;Branch if active (2/3)
;
; - If no DRQ is sensed, the other possibilities are:
; 1- A LBA Write has occurred and the interrupt was generated after the transfer.
; 2- A Verify operation has occurred and the interrupt was generated after the verify.
; So we check for these two options and branch accordingly.
;
                BBS2    MATCH,IDE_WRIT_BLK      ;If Bit 2 set, Write operation (5)
                BBS1    MATCH,IDE_VRFY_BLK      ;If Bit 1 set, Verify operation (5)
                BRA     REGEXT01                ;Exit ISR handler (3)
;
IDE_READ_BLK                            ;IDE Read a Block of data
;
;Note: Arrival here means that the DRQ bit in the status register is active.
; This implies that:
;  1- A LBA Block Read is in progress. If so, the data transfer will be handled below.
;     This also handles multiple LBA Reads and manages the pointers and such. It also
;     clears the LBA Read bit in the MATCH Flag when completed.
;
;  2- A LBA Block Write with multilpe blocks is in progress. If so, the actual data
;     transfer is handled via the IDE WRITE Block routine. An interrupt is generated
;     at the end of each LBA transfer, so that is monitored here and the LBA Write bit
;     in the MATCH Flag is cleared when there are no more blocks to transfer.
;
;Also realize that this ISR will be executed every time the DUART generates an interrupt.
; This will happen every 10ms for the Jiffy-Clock timer and for character transmit and receive.
;
                BBR3    MATCH,REGEXT01  ;If Bit 3 clear, IDE Write (5)
;
LBA_XFER        LDA     IDE_ALT_STATUS  ;Get Status (clears IRQ) (4)
                AND     #%00001000      ;Check for DRQ (2)
                BEQ     IDE_RD_DONE     ;If not active, done, exit (2/3)
;
IDE_RD_RBLK
                LDA     IDE_DATA        ;Read low byte (high byte in latch) (4)
                STA     (BIOS_XFERL)    ;Store low byte (5)
                INC     BIOS_XFERL      ;Increment pointers (5)
                BNE     IDE_RD_BLK1     ; (2/3)
                INC     BIOS_XFERH      ; (5)
IDE_RD_BLK1
                LDA     IDE_16_READ     ;Read high byte from latch (4)
                STA     (BIOS_XFERL)    ;Store high byte (5)
                INC     BIOS_XFERL      ;Increment pointers (5)
                BNE     LBA_XFER        ;Loop back to Xfer, saves 3 clock cycles (2/3)
                INC     BIOS_XFERH      ; (5)
IDE_RD_BLK2
                BRA     LBA_XFER        ;Loop back till no more DRQs (3)
;
IDE_RD_DONE     DEC     BIOS_XFERC      ;Decrement Block Count to transfer (5)
                BNE     IDE_ALL_DONE    ;Branch around Flag Reset until all blocks moved (2/3)
                RMB3    MATCH           ;Clear Read Block flag (5)
;
IDE_ALL_DONE    LDA     IDE_ALT_STATUS  ;Get Alternate Status Register (4)
                STA     IDE_STATUS_RAM  ;Save it to RAM location (3)
REGEXT01        JMP     (VECINSRT0)     ;Exit ISR handler (6)
;
IDE_WRIT_BLK                            ;IDE Write a Block of data
                LDA     BIOS_XFERC      ;Check Block Count to transfer (3)
                BNE     IDE_ALL_DONE    ;Branch to exit if more blocks need to be moved (2/3)
                RMB2    MATCH           ;Clear Write Block flag (5)
                BRA     IDE_ALL_DONE    ;Branch and finish ISR (3)
;
IDE_VRFY_BLK                            ;IDE Verify a Block of data
                RMB1    MATCH           ;Clear Verify Block flag (5)
                BRA     IDE_ALL_DONE    ;Branch and finish ISR (3)
;
;**************************************************************************************************

   INX
   CPX #$00
   BNE
   ...