Joined: Thu May 28, 2009 9:46 pm Posts: 8403 Location: Midwestern USA
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Sean wrote: BigDumbDinosaur wrote: Sean wrote: To be fair, every definition I've ever seen for implied instructions are any instruction whose operand is implied. What would the operand be for any of the push instructions?One could easily argue these are actual instructions with two implied operands, the register and the stack. But since they're not specified, they are implied. Please read section 3.5.22 on page 22 of the latest 65C816 data sheet. Here’s part of what it says:Quote: Stack (s) addressing refers to all instructions that push or pull data from the stack, such as Push, Pull, Jump to Subroutine, Return from Subroutine, Interrupts, and Return from Interrupt. (Emphasis added.)
In other words, PHA, PLD, RTI, etc., are stack addressing mode instructions, not implied. Section 4.10 on page 17 of the latest 65C02 data sheet says the same thing.
In the 65xx architecture, the implied addressing mode refers to instructions that act solely on registers. That is, an implied instruction does not perform a memory or I/O access. The 65C816’s implied mode instructions are CLC, CLD, CLI, CLV, DEX, DEY, INX, INY, NOP, SEC, SED, SEI, TAX, TAY, TCD, TCS, TDC, TSC, TSX, TXA, TXS, TXY, TYA, TYX, XBA and XCE.
Incidentally, ASL, DEC, INC, LSR, ROL and ROR, when used on the accumulator, are said to be accumulator addressing mode instructions. In the official MOS Technology assembly language standard, that addressing mode is specified in source code by using the letter A as the operand—A is a reserved symbol that cannot be defined in source code. For example, to right-shift the accumulator, you would write LSR A. Many assemblers assume if there is no operand then accumulator addressing applies.
_________________ x86? We ain't got no x86. We don't NEED no stinking x86!
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