A simple ISR for uart 16c550 + 65c816 is here:

http://65xx.unet.bz/c16sw/

Uart work in fifo mode, can handle these baud rates: 38,400 - 57,600 - 115,200 - 230,400 (uart clocked at 3.6864Mhz), and allow both hardware handshake (through standard null-modem or uplink cable) and software handshake (through xon/xoff control character).

Simple user callable routines for open serial port, put a byte in output buffer, fetch a byte from input buffer, are given.
I maked test with long pattern sequences and all work fine at any of four selectable baud rate, with both of null-modem cable type, and both handshake.

At 230,400 bps i used a trigger level = 14 for rx fifo interrupt, and work fine, but maybe in a busy system need to use the trigger level = 8.

Marco

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http://65xx.unet.bz/ - Hardware & Software 65XX family

and click on "16C550 I.S.R." at the left edge. (The URL does not take you directly to it.)

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I guess this seems like as appropriate a thread as any, but I'm confused by the terminology most of the 16C550 literature uses regarding the FIFO status bits. Every place I read talks about these bits in terms of the FIFOs being "full," but they seem to mean "not empty" most of the time. Based on example code here and elsewhere, I think that the behavior is as follows:

Status register bit 0 is set whenever there's unread characters in the receive buffer.
Status register bit 5 is set whenever there's room in the transmit buffer.
Status register bit 6 is set whenever the transmit buffer and shift register are completely empty.

This would seem like the logical way for these to work, but can someone confirm this for me? The references I've read are very ambiguously-phrased.