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jeffythedragonslayer
PostPosted: Mon Oct 25, 2021 2:38 am 
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Are there differences in the capabilities of the X and Y registers, or can the opcodes that access them be substituted for each other in any 6502 asm source without any ill effects?
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barrym95838
PostPosted: Mon Oct 25, 2021 2:46 am 
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The instructions and modes that come to mind are TSX, TXS, zp,X, zp,Y, (zp,X) and (zp),Y. In those six instances you can't substitute the other index register and wind up with a legal instruction. The 6502 doesn't allow things like LDX abs,X or LDY abs,Y either. There are more examples on the 'c02 and 'c816, but I'll leave those as an exercise for the reader.

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GARTHWILSON
PostPosted: Mon Oct 25, 2021 4:01 am 
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Note especially the (ZP,X) and (ZP),Y, where X is used for pre-indexed indirect addressing and Y is used for post-indexed indirect addressing.

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BigDumbDinosaur
PostPosted: Mon Oct 25, 2021 4:15 am 
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jeffythedragonslayer wrote:
Are there differences in the capabilities of the X and Y registers, or can the opcodes that access them be substituted for each other in any 6502 asm source without any ill effects?

As I've said before, there is an excellent programming manual by Eyes & Lichty that goes into great detail about register usage. Please read it! And if you don't have a copy, go to the WDC website and look under documentation.

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GARTHWILSON
PostPosted: Mon Oct 25, 2021 4:20 am 
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BigDumbDinosaur wrote:
there is an excellent programming manual by Eyes & Lichty that goes into great detail about register usage... if you don't have a copy, go to the WDC website and look under documentation.

https://wdc65xx.com/Programming-Manual/
This is definitely the best 65xx programming manual available, and a must-have for every 65xx programmer! It starts with the basics, followed by architecture, the CMOS 65c02's many improvements over the original NMOS 6502 including added instructions and addressing modes and fixing the NMOS's bugs and quirks, and then the natural progression to the 65816; a thorough tutorial, writing applications, then very detailed and diagrammed information on all 34 addressing modes, at least a page of very detailed description for each instruction, with info on every addressing mode available for that instruction, then instruction lists, tables, and groups, of all 255 active op codes, plus more. 469 pages. From Western Design Center. (.pdf) Note: There were many problems with the earlier .pdf version that were not in the original paper manual; but in late March 2015, WDC scanned and OCR'ed the paper manual and posted the new, repaired .pdf.

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BigDumbDinosaur
PostPosted: Mon Oct 25, 2021 4:27 am 
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GARTHWILSON wrote:
BigDumbDinosaur wrote:
there is an excellent programming manual by Eyes & Lichty that goes into great detail about register usage... if you don't have a copy, go to the WDC website and look under documentation.

https://wdc65xx.com/Programming-Manual/
This is definitely the best 65xx programming manual available, and a must-have for every 65xx programmer! It starts with the basics, followed by architecture, the CMOS 65c02's many improvements over the original NMOS 6502 including added instructions and addressing modes and fixing the NMOS's bugs and quirks, and then the natural progression to the 65816; a thorough tutorial, writing applications, then very detailed and diagrammed information on all 34 addressing modes, at least a page of very detailed description for each instruction, with info on every addressing mode available for that instruction, then instruction lists, tables, and groups, of all 255 active op codes, plus more. 469 pages. From Western Design Center. (.pdf) Note: There were many problems with the earlier .pdf version that were not in the original paper manual; but in late March 2015, WDC scanned and OCR'ed the paper manual and posted the new, repaired .pdf.

Despite all my years of writing 65xx assembly language, I still refer to that manual now and then to make sure my thinking is straight. This has become especially important in my geriatric years. :shock:

Seriously, there is no excuse for a 6502 programmer to not have that manual handy at all times. I printed and bound a hardcopy so I wouldn't have to keep looking at the PDF.

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GARTHWILSON
PostPosted: Mon Oct 25, 2021 4:35 am 
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I bought my paper copy in the mid-1990's, when you couldn't get it online yet (in fact, the web was in its infancy, and I think I still had the GEnie service, all text, probably still accessed on my first, 2400bps modem, and was not connected to the WWW). I still refer to the manual quite frequently.

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BigDumbDinosaur
PostPosted: Mon Oct 25, 2021 5:11 am 
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GARTHWILSON wrote:
I bought my paper copy in the mid-1990's, when you couldn't get it online yet (in fact, the web was in its infancy, and I think I still had the GEnie service, all text, probably still accessed on my first, 2400bps modem, and was not connected to the WWW). I still refer to the manual quite frequently.

I never used GEnie. They charged too much for what they were offering. In those days, I was more likely to dial into a BBS than a commercial service.

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jeffythedragonslayer
PostPosted: Mon Aug 22, 2022 12:46 am 
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Matt and I started this cheat sheet on the differences between all the registers: https://wiki.superfamicom.org/register-capability-table
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GARTHWILSON
PostPosted: Mon Aug 22, 2022 1:12 am 
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jeffythedragonslayer wrote:
Matt and I started this cheat sheet on the differences between all the registers: https://wiki.superfamicom.org/register-capability-table

In the first row, the "?" in the "Program Counter" column can be replaced with "16-bit" like the "Stack Pointer" column.

The TSA in the "can be transferred to A?" row and "Stack Pointer" column should be augmented with TSC, the preferred mnemonic, as it's always 16-bit regardless of the size you have the accumulator set to.

Why is the BRA in the program-counter column for the "can be decremented by one?" row?

The "PL* when * is an 8-bit register" and "PH* when * is an 8-bit register" imply that PL* and PH* don't apply when the register is 16-bit, which is incorrect. For example PHY will push two bytes if the index registers are set to 16-bit.

In the "Accumulator" column for the "can be decremented by one?" row, you could add the DEA (DEcrement Accumulator) mnemonic which many (most?) assemblers recognize.

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BigDumbDinosaur
PostPosted: Mon Aug 22, 2022 1:53 am 
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jeffythedragonslayer wrote:
Matt and I started this cheat sheet on the differences between all the registers: https://wiki.superfamicom.org/register-capability-table

You have several references on that page with errors. For example, PHB is not an implied addressing mode instruction; it uses stack addressing, same as PHA, PHD, PHK, etc. Implied mode instructions act internally on one or two registers and do not access memory or I/O. If an instruction accesses memory or I/O it is not implied addressing.

We've had this discussion before, but evidently you don't seem to understand the disservice you’re performing by posting inaccurate information. Again, I strongly recommend you read the Eyes & Lichty manual before making and publishing charts with errors in them. You are not doing anyone any favors posting bad info!

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Sean
PostPosted: Mon Aug 22, 2022 2:38 am 
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BigDumbDinosaur wrote:
jeffythedragonslayer wrote:
Matt and I started this cheat sheet on the differences between all the registers: https://wiki.superfamicom.org/register-capability-table

You have several references on that page with errors. For example, PHB is not an implied addressing mode instruction; it uses stack addressing, same as PHA, PHD, PHK, etc. Implied mode instructions act internally on one or two registers and do not access memory or I/O. If an instruction accesses memory or I/O it is not implied addressing.


To be fair, every definition I've ever seen for implied instructions are any instruction whose operand is implied.
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BigDumbDinosaur
PostPosted: Mon Aug 22, 2022 2:48 am 
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Sean wrote:
To be fair, every definition I've ever seen for implied instructions are any instruction whose operand is implied.

What would the operand be for any of the push instructions?

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Sean
PostPosted: Mon Aug 22, 2022 3:23 am 
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BigDumbDinosaur wrote:
Sean wrote:
To be fair, every definition I've ever seen for implied instructions are any instruction whose operand is implied.

What would the operand be for any of the push instructions?


One could easily argue these are actual instructions with two implied operands, the register and the stack. But since they're not specified, they are implied.
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BigDumbDinosaur
PostPosted: Mon Aug 22, 2022 5:16 am 
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Sean wrote:
BigDumbDinosaur wrote:
Sean wrote:
To be fair, every definition I've ever seen for implied instructions are any instruction whose operand is implied.

What would the operand be for any of the push instructions?

One could easily argue these are actual instructions with two implied operands, the register and the stack. But since they're not specified, they are implied.

Please read section 3.5.22 on page 22 of the latest 65C816 data sheet. Here’s part of what it says:

Quote:
Stack (s) addressing refers to all instructions that push or pull data from the stack, such as Push, Pull, Jump to Subroutine, Return from Subroutine, Interrupts, and Return from Interrupt.

(Emphasis added.)

In other words, PHA, PLD, RTI, etc., are stack addressing mode instructions, not implied. Section 4.10 on page 17 of the latest 65C02 data sheet says the same thing.

In the 65xx architecture, the implied addressing mode refers to instructions that act solely on registers. That is, an implied instruction does not perform a memory or I/O access. The 65C816’s implied mode instructions are CLC, CLD, CLI, CLV, DEX, DEY, INX, INY, NOP, SEC, SED, SEI, TAX, TAY, TCD, TCS, TDC, TSC, TSX, TXA, TXS, TXY, TYA, TYX, XBA and XCE.

Incidentally, ASL, DEC, INC, LSR, ROL and ROR, when used on the accumulator, are said to be accumulator addressing mode instructions. In the official MOS Technology assembly language standard, that addressing mode is specified in source code by using the letter A as the operand—A is a reserved symbol that cannot be defined in source code. For example, to right-shift the accumulator, you would write LSR A. Many assemblers assume if there is no operand then accumulator addressing applies.

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