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 Post subject: 65C02 instruction sets
PostPosted: Sat May 16, 2020 6:16 pm 
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A recent post, starting around here: viewtopic.php?f=2&t=6129#p75750 had some discussion around different CMOS instructions included or not depending on what vendor produced the CPU. I searched my own archives (digital and paper) and have attached all of the various CMOS datasheets I have. These include my original Rockwell R65C02 datasheet from 1984 (which I scanned in) and some others including NCR, California Micro Devices (CMD) and an older (circa 2002) WDC datasheet. Oddly, the newer WDC don't include the number of clock cycles required per instruction, despite the frequent updates they've made (most recent being February of 2020).

In short, Rockwell parts have all of the SMBx, RMBx, BBSx and BBRx as do the WDC parts, however the NCR ad CMD parts do not. Only the WDC parts have WAI and STP. Hope the attached datasheets are useful to some folks out here.

Referencing the post above, I would tend to agree that adding these specific instructions (SMBx, RMBx, BBSx and BBRx) to a C Compiler would likely be of little value and probably more of a challenge to use. However, I have found them quite useful for lots of coding since they came out in the 80's. As many programmers have used Page Zero locations as flag bytes or bits, the standard 6502 instruction set requires more coding and execution time when doing so. The newer instructions make it easy to set or clear individual bits in a Page Zero location as well and test and branch on them, without altering the tested bit or CPU processor flags. It saves memory space and execution time in most cases. It also allows a single Page Zero location to be easily used for 8 separate flags.

Attachment:
65C02.pdf [427.28 KiB]
Downloaded 129 times

Attachment:
g65sc02.pdf [664.04 KiB]
Downloaded 85 times

Attachment:
W65C02S.pdf [1.72 MiB]
Downloaded 85 times

Attachment:
Rockwell-R65C02.pdf [13.05 MiB]
Downloaded 119 times

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PostPosted: Sat May 16, 2020 6:24 pm 
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A related thread aimed to catalogue all the subsets and supersets of instruction sets:
Overview of 6502-like cores, hard, soft, partial, overblown


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PostPosted: Sat May 16, 2020 6:27 pm 
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floobydust wrote:
... I would tend to agree that adding these specific instructions (SMBx, RMBx, BBSx and BBRx) to a C Compiler would likely be of little value and probably more of a challenge to use. However, I have found them quite useful for lots of coding since they came out in the 80's. As many programmers have used Page Zero locations as flag bytes or bits, the standard 6502 instruction set requires more coding and execution time when doing so. The newer instructions make it easy to set or clear individual bits in a Page Zero location as well and test and branch on them, without altering the tested bit or CPU processor flags. It saves memory space and execution time in most cases. It also allows a single Page Zero location to be easily used for 8 separate flags ...

I agree; they aren't just for I/O in ZP, as was implied elsewhere. I have seen many code examples from the NMOS era that would be able to benefit from them in the manner you describe, but I still avoid them in my own creations for eccentric personal reasons.

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