Hi guys

I'm about 3/4's of the way through writing the simulator part of my 65C02 assembler and am currently coding the opcodes.
I've done a large number of them (LDA, STA, EOR, AND and lots more), but have run into a snag: I'm now trying to write the code for RTI and RTS. RTI is the main issue as, when an interrupt fires on a 65C02, the program counter followed by the status register is pushed on to the stack.
Does anyone know the order in which the program counter is pushed? I.e. LSB then MSB or vice versa? I cannot seem to find any information which specifies this.
I have tried firing up BeebEm - a BBC Micro emulator (a very faithful one) - and tried some tests, but of course the MOS (firmware/BIOS) does not contain the commands as they're hard coded into the 65C02 I believe. I have also had a look at an old copy of "Programming the 65816" but so far not spotted the info there either.

BTW I could just code this anyway I like and ensure the interrupt simulation matches, but I'd rather get it the right way around.

Any advice would be most welcome

In the 65C02, the order of pushes following an interrupt is PC high, PC low and SR. Following the stack activity, the I-bit is set in SR and the PC is loaded from $FFFE-$FFFF. Upon executing RTI, the 'C02 pulls SR, followed by PC low and then PC high.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Exactly the info I needed - thanks . I was just trying to reverse engineer the JSR instruction figuring that the order would be the same LSB / MSB wise

The '816 data sheet has more info in this regard than the '02 data sheet does. At http://6502.org/documents/datasheets/wdc/, at the bottom of the page, is the '816 data sheet, http://6502.org/documents/datasheets/wd ... 3_2010.pdf . See table 5-7 (which is many pages). It tells what happens in every cycle of every instruction. You want part 22a on page 43. Omit the cycle that pushes the program bank register since you're on the '02 and not the '816.


If you're on the fixed version, the info is in figure 13.2, on p.279.

It's also in my 6502 interrupts primer.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Bear in mind - you may know this well - that whereas RTI uses the value it finds on the stack, RTS has to increment the value.
http://visual6502.org/JSSim/expert.html ... f&steps=66

As Garth noted, this info can be found in a WDC document. However, a far more readable reference is Appendix A of the MCS6500 Family Hardware Manual which, like the WDC doc, is on file in the 6502.org docuument archive. Recommended!

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I'll defo have a read - thanks guys.
With regards the RTS instruction: I had assumed that the return address was modified before being pushed on to the stack. Time to modify my code methinks!

JSR / RTS now working as intended: JSR pushes the address of the last byte of the JSR+param instruction combo on to the stack and the RTS pulls that down and adds one it and sets that as the program counter.
I've also crowbared my simulator exit system into that as well so that there is a way 'out' of the simulator once a program has started. Upon initialisation the simulator pushes $FFFC on to the beginning of the stack so that if an RTS occurs and that is the return address then the Simulator ends and returns control to the assembler. I figure the vast majority of code will not RTS to the reset vector deliberately. Of course, it does rely on the stack not becoming corrupted and/or stack pushes/pulls & jsr/rts/rti are done correctly. Worse case the user can press Escape to abort.

RTS will increment it to $FFFD, which is not what you intended. It wouldn't matter though, because there's no executable code there.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I accounted for that . It checks the address before the incrementation occurs.

I would've chosen the value $DEAD

Mike B.

Or detects two sets of RTS one after the other and if it picks up $DEAD $BEEF we know to exit

When one is DEADBEEFing memory, does one use $EFBEADDE for a tastier 8-bit hex dump that looks like

or $DEADBEEF, which on our little-endian 6502 looks like

What is a DEEF BEAD?

When one initializes a machine, filling unused memory with some pattern both tests the memory and leaves a textured canvas where anomalies (e.g. "something wrote something HERE??") can often be visually discovered in the scrolling hex dumps. For example, at power-up, the Commodore PET writes $55 and then $AA to every byte of RAM, as a memory test and counter