Hi All,

I'm wondering what everyone else does to handle interrupts. Right now since there is only one IRQ line (not including the NMI line), I'm or'ing together several potential things that could request an interrupt which then requires me to query each interrupt connected device to see which one did it to execute their specific interrupt handler.

I was wondering if there was a better way to handle this in software/hardware as I waste a decent amount of time dealing with the interrupt, and of course the issues of dealing with multiple interrupts at the same time.


ps - if I could I would cross post this in hardware, but I don't think there is a way to cross post...
-T

_________________
-Tony
KG4WFX

You could do this..

Connect all the interrupts to a 1 of n priority encoder and connect the <>0 output of the encoder to the IRQ line. Make a port so you can read the coded output of the priority encoder.

Now when there's an interrupt you just read the port and use that as an index to the routine for that interrupt.

There is a 74 series chip that does most of this in one package. I'll have to look it up though.

Lee.

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What's an additional VIA among friends, anyhow?

Garth: Interesting, I'll be looking forward to the article you will have on interrupts. I never really had to think of so many before in the past, so this is kind of new to me.

Lee: If you happen to find out what that IC is, please let me know, I'll probably start searching thru my nte book tonight, hopefully I'll come across it....

_________________
-Tony
KG4WFX

Hi Tancor,

I believe the IC Lee is referring to is the 74LS148 Priority Encoder.

It takes 8 (active low) inputs and provides a 3 bit output. There is another output (GS) that is active low anytime there is an active input, which can connect to IRQ or NMI. It can also be cascaded to provide 16 inputs.

You can find the datasheet at the Fairchild Semiconductor website:
http://www.fairchildsemi.com/

Hope this helps!

Daryl

Yup, 74LS148 or 74LS248 (I think). So when you get an interrupt you do ..



This easily handles up to 8 interrupts. When one interrupt is done if there are any lower priority interrupts still pending IRQ will be held low and the interrupt routine will be called again to handle that one. This continues until no interrupting sources remain.

I'm sure an arcade board used something similar to handle sprite-sprite, sprite-character, sprite-background, timer and input interrupts.

Lee.

If you just wire the chip one bit over and use a 65c02, you could shorten that to:


Eliminating the AND# may also be possible if you work the circuit to deliver 0's in the other bits when you read that address. Then it could become:

The '248 is NOT a priority encoder! The '248 (and '247) are BCD-to-7-segment decoder/drivers!
The '148 is a 8-line to 3-line priority encoder.
The '147 is a 10-line to 4-line priority encoder.

Anyway, here are a couple of other ideas you could try. I haven't tried these myself, so you may want to experiment before going hog wild with the soldering iron. The following signal names are used below:

An = bit n of the (65C02) address bus
ADn = bit n of the ROM address input
Yn = bit n of the '148 output

Say, for example, you have a 4k x 8-bit ROM mapped to $F000-$FFFF, where A11-A0 is connected to AD11-AD0. The idea is to use a 32k x 8-bit ROM, connecting AD11-AD0 to A11-A0, and AD14-AD12 to Y2-Y0. Now you have eight 4k chunks of ROM. Make all eight chunks identical EXCEPT for the locations that map to $FFFE and $FFFF, and now you have eight vectors for eight different interrupt sources and you don't need to determine the interrupt source in software at all. Of course, you'll only be able to access one interrupt vector at time with, say, a LDA $FFFE, but how often do you need to read interrupt vectors with LDA? The main downside to this approach is that you may need a large ROM.

Idea number two is to create a signal that I'll call FFFEB which is low when you are accessing address FFFE or FFFF and high otherwise. Basically, FFFEB is:

FFFEB = NOT (A1 AND A2 AND A3 AND ... AND A13 AND A14 AND A15)

or if you have a newfangled 65C02 with the VPB signal:

FFFEB = VPB OR (NOT (A1 AND A2))

then use the FFFEB signal to modify the ROM address you read from, as follows:

AD1 = A1 AND (FFFEB OR Y0)
AD2 = A2 AND (FFFEB OR Y1)
AD3 = A3 AND (FFFEB OR Y2)
AD4 = A4 AND FFFEB

Connect all other ADn lines to An. Then the vector for interrupt source N is at $FFE0 + N * 2. The 10 bytes at $FFF0-$FFF9 will be unused, but maybe you can find something to put there.

If the above is confusing, feel free to post or e-mail me.

Ok so perhaps not '248, there is another 8 to 3 line encoder but I forget it's part #

Nice ideas on hardware vectoring but what happens if a higher priority interrupt arrives between fetching the first byte of the vector and fetching the second byte?

Lee.

How about latching the priority encoder with the processor SYNC signal so that it can't change mid-instruction?

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Andrew Jacobs
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The '348 is an 8 to 3 line priority encoder with tri-state outputs. There is also a '748 and '848 (from Motorola) which are equivalents of the '148 and '348, respectively, and are were designed to minimize glitches on the GS output pin.



If the interrupt handlers are short, start all of them on the same page and all of the high bytes will be the same. If the interrupts handlers are long, you could start all of them on page boundaries and all of the low bytes will be the same. In fact, with all of the low bytes the same, you could use FFFFB (low when accessing $FFFF ONLY, high otherwise) instead of FFFEB in the second idea above and move everything down one bit and map the high bytes to $FFF0-$FFF7 and save a few bytes. In the case where all of the high bytes are the same, change FFFEB so that it is low when accessing $FFFE ONLY, and high otherwise. Move everything down one bit, but for AD0 use:

AD0 = A0 OR ((NOT NewFFFEB) AND Y0)

Then the low bytes will be mapped to $FFF0-$FFF8. If the interrupts are asynchronous and could, for example, change in the middle of the cycle that the low byte is fetched (in the case where all of the high bytes are the same), then the latch (or a flip-flop) that someone else suggested is probably a good idea. In this case you could probably use the processor clock rather than SYNC, since you'll only need a stable value for one clock cycle.

Found it, 74LS348 - 8 input priority encoder with tri state outputs.

Easier to interface as you wouldn't need external data bus buffers.

Lee.

for my own SBC, I only have 2 types of interrupt chips coming in, so its easier with my little idea. I use a 6522 and the IRQ pin also can go out, so the interrupts are either from that 6522 or from otside. From the6522, i the irq routine, I merely copy the status flag over to a memory location and call it the interrupt location. The bit will tell exactly what caused the interrupt from the 6522, and if thevalue is 0, then the interrupt is from outside. I figure if I have multiple outside IRQ sources, if I use 6522s, I can always check the flag registers which takes some time, or go the priority route and define accordingly....

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_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Lee, in terms of 6502 usage, I have yet to see an arcade board use multiple interrupt inputs, there wopuld usually only be a single one. On some laster 68000 games, there might be some priority encoding, the only ones I DID actually see in circuit for prioritzing interrupts would be Sky Shark and Twin Cobra.

The Bally pinball MPU is kind of bananas for interrupots, though. It uses 2 6821s, a 6800 cpu and 2 seperate interrupt inputs, a 120 hz zero crossing fromthe AC in the cabinet, and a 555 time for the display interrupts, something like 300 hz.

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"My biggest dream in life? Building black plywood Habitrails"