I have started an AVR->6502 reassembler.
you can track changes here:
https://github.com/tweakoz/zed64/tree/master/reasmMy intentions for this are as a learning experience, and so I can use avr-g++
to generate code for my fpga based computer I am designing.
I certainly do not intend on using c++ code on 6502 for performance critical
situations, but since I am primarily a c++ programmer these days, I just
find it convenient and fast for noodling around, and I have used minimalist embedded friendly c++ on
Arduino's with some success..
I was kind of inspired by Jason Turners x86->6502 video at:
https://www.youtube.com/watch?v=nLv_INgaLq8I figured the AVR->6502 approach should pan out fairly well, since AVR is 8 bit and avr-gcc has a decent sized community supporting 8bit targeted gcc which can be leveraged via reassembly. I do realize it would likely be more efficient at runtime to do the 6502 code generation in the compiler. I also know that there is an effort underway on gcc-6502 already...
I need instant gratification and I was able to get the 1st pass of the reassembler working in a few days. I still have more work to do in making it functional with a variety of relevant c++ source. I do not ever intend on supporting heap allocation or anything which can not actually run on a small device.
It works by mapping independent avr opcodes onto 1 or more 6502 opcodes - utilizing zero page as avr registers. Hardly runtime efficient - it is what it is...
The reassembler itself is written in python and expects avr assembly source files like that which would be generated from avr-gcc (gnu-assembler). It generates 6502 assembly in ca65 (cc65 assembler) format.
mtm
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