I noticed the comments don't appear to show up when copying everything out. Well, the first comment does but none of the others.

Unfortunately, I can't replicate that, either in Chromium or Firefox. I tried the multiple comments with blank lines and around the various display types as well, and it all copies.

Is there anything notably funky going on with how/where the comments are, or would you want to PM me the .wfdis file of the workspace you can't copy out?

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WFDis Interactive 6502 Disassembler
AcheronVM: A Reconfigurable 16-bit Virtual CPU for the 6502 Microprocessor

Hello, I think I may have found a small bug. I was disassembling this code, which is "65C02 with bit operations":

Address: $E4DD
6F 15 12 20 8A E7 20 F9 E6 20 AB E7 20 61 E7 20 F6 E0 20 06 E5 0F 11 0A F7 12 A5 12 8D 12 41 20 78 E6 6C 06 01

I get a BBS7 opcode where there should be an SMB7.



Also, when I load a saved file that using "65C02 with bit operations", it seems to always revert to normal 6502. I just wanted to let you know these things I found; I have worked around them no problem. Thanks for the cool disassembler.

Ben:

Also, should the BBS instructions not be BBR instructions?

In my instruction tables, the msb of the Rockwell instructions indicates the polarity of the test or the set operation. I checked my tables against those in the Rockwell R65F1x processor family data sheet.

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Michael A.

Referring to Eyes/Lichty:

0F to 7F is BBR0 to BBR7.
8F to FF is BBS0 to BBS7.
07 to 77 is RMB0 to RMB7.
87 to F7 is SMB0 to SMB7.

I have a Rockwell 'C02 datasheet that agrees with Eyes/Lichty as cited by Chromatix.

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Oof, I had fixed the display of the bit operations above, but hadn't uploaded it because of other work also being done back then. They all ended up with a BBS name before. It's fixed in this new version.

HuC6280 CPU support added now, which is the 6502 derivative from the PC Engine/TurboGrafx-16. Besides a number of new instructions, it also maps zeropage to $20xx and stack to $21xx, necessitating some more flexibility in the CPU definitions.

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WFDis Interactive 6502 Disassembler
AcheronVM: A Reconfigurable 16-bit Virtual CPU for the 6502 Microprocessor