Interesting! I see the FPGA in that case (from the Turbo Chameleon 64 project) is a Cyclone II with 66 block RAMs, giving a maximum width of 1188 bits. That's pretty similar to the LX9 in the Matchbox copro, which has 32 block RAMs and a maximum width of 1152 bits.
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The simulation using a modest 100 Mhz clock can process about 25 million rows per second. Which translates to 12.8 giga cells updated per second or over 50 thousand grid iterations per second.
That's blazingly fast, but on a grid limited to normal video resolutions... I'm quite fond of the very large universes possible with a list-based or tile-based life. Then we'd be back to the constraints of RAM speed... the Matchbox has the advantage of 32 bit wide pSRAM, but the 55nS access limits the cycle time to 18MHz. I'm not sure if Life's locality would allow us to get some advantage by mixing on-chip and off-chip memory. Surely some advantage.
A hash life usually uses enormous memory structures. I wonder if a mini hash life could usefully fit the hashes into the 64k of on-chip RAM. Or if hash access has some locality and we can use the on chip RAM as a form of cache for tables in the 2Mbyte pSRAM.
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