barrym95838 wrote:
I figured that it was more appropriate to ask my questions in this thread rather than subject the
other thread to more off-topic pollution.
Wow, revival of an 11-year-old topic! That's partly why we keep the archives though-- to avoid having to repeat stuff, and to review what was learned in the past.
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Sub-topic 1: The Rockwell 'c02 seems to use 32 opcodes to set, reset, and test-and-branch individual zero-page bits. Does anyone here use these? It seems to me that they would be very fast and compact for flags, but nearly useless for I/O, unless port(s) were mapped into zero-page, a la 6510. Does anyone have any commented code snippets to share, showing how these guys work? (links would suffice)
There were some 6502-based microcontrollers with I/O in ZP which took advantage of BBS, BBR, SMB, and RMB. I have never had I/O in ZP, so I have had no real use for these. I think it would be more useful to have them for absolute addressing only than to have them for ZP addressing only. If you have the op codes available on the 65m32, I'd say go for it.
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Sub-topic 2: The WDC 'c02 seems to use just four opcodes to test-and-set and test-and-reset up to 8 bits anywhere in RAM. I know that Garth and BDD have used these, but I would be interested in knowing if there is a good reason for them only changing the Z flag. Why not N and V as well, like their close cousin, BIT? I'm guessing that there is a reason, but is it to make the hardware less complicated, or the hypothetical software using it less complicated, or both, or neither? Does anyone have any commented code snippets to share, showing how these guys work? (links would suffice)
I don't know why it doesn't do N & V as well. As I think about my own uses for TSB & TRB, I don't see much extra need for affecting N & V at the same time, probably because I have never tested bits
while setting or clearing bits.
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Sub-topic 3: The WDC and Rockwell versions don't exist together on any design, as far as I know, due to functional overlap. If a hypothetical processor design implemented the Rockwell-like set with full-RAM addressing, do you guys think that it would be preferable to the WDC-like set?
WDC did add the Rockwell instructions to their '02 over 20 years ago, so they do have both. They do not reside in the same columns in the opcode table. However, if the instructions couldn't coexist, then I'd say the RMB, SMB, BBS, and BBR would be preferable, as long as they're not limited to ZP or DP. I have used TSB & TRB for more than one bit at a time though, which SMB & RMB cannot do. An example is at
http://wilsonminesco.com/6502primer/SPI.ASM .