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PostPosted: Mon Jan 25, 2021 6:38 pm 
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I am looking for a fast way to copy a variable amount of data between two banks (basically like a file read or write) on the 65816.

I am not sure I fully understand how the DBR works, but as I read it, consecutive reads/writes would all go to the same bank, except if I change the DBR in between, right?

So the fastest thing I came up with was basically a long read (3-byte address, indexed) followed by a long write (3-byte address, indexed), using self-modifying code to update the read and write addresses appropriately... right?

Would this work in emulation mode too? (i.e. are the long indexed addressing modes available, and not truncated to bank 0)?

Thanks
André

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PostPosted: Mon Jan 25, 2021 7:06 pm 
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It sounds to me as if MVP/MVN might work for you:

http://www.6502.org/tutorials/65c816opcodes.html#6.6


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PostPosted: Mon Jan 25, 2021 8:13 pm 
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rwiker wrote:
It sounds to me as if MVP/MVN might work for you:

http://www.6502.org/tutorials/65c816opcodes.html#6.6


This. 7 cycles per byte after setup.

Even for copying data in the same bank, although I've not yet worked out the minimum number of bytes to copy vs. a simple loop when the overhead of setting the registers for the MVN/MVP beats the simply copy loop...

And one thing to remember as it's not always obvious is that the DBR is left set to that of the destination bank.

-Gordon

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PostPosted: Mon Jan 25, 2021 8:35 pm 
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fachat wrote:
I am looking for a fast way to copy a variable amount of data between two banks (basically like a file read or write) on the 65816.

I am not sure I fully understand how the DBR works, but as I read it, consecutive reads/writes would all go to the same bank, except if I change the DBR in between, right?

To the maximum extent possible, I avoid messing with DB, since it can only be loaded and saved via the stack. Basically, your two options for mass-copying data are long indirect addressing or use of the block-copy instructions that are unique to the 65C816.

In native mode, the MVN and MVP instructions will copy up to 64KB chunks of memory, either intra- or inter-bank. Use MVN when the source and destination addresses are in the same bank and the destination address is lower than the source address, or when the destination is in a different bank than the source. Use MVP when the source and destination addresses are in the same bank and the destination address is higher than the source address. Both instructions will copy at the rate of one byte per seven clock cycles, which is much faster than achievable by rolling your own with indirect addressing.

Note that MVN and MVP are interruptible instructions, so your interrupt handlers must preserve the accumulator and index registers, as well as DB. Also, DB should be pushed before executing MVN or MVP and subsequently pulled afterward, since as Gordon noted, DB is clobbered during the copy procedure.

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So the fastest thing I came up with was basically a long read (3-byte address, indexed) followed by a long write (3-byte address, indexed), using self-modifying code to update the read and write addresses appropriately... right?

If you want to "manually" copy you should use long indirect indexed addressing, which is notated in compliant assemblers as [<dp>],y. <dp> refers to three consecutive locations on direct page in which an address is set in customary little-endian format—<dp>+2 is the bank. With the index registers set to 16 bits, you can copy up to 64KB without having to touch the direct page pointers. Unlike copying with MVN and MVP, this method can overlap bank boundaries, hence treating the 65C816's address space as linear.

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Would this work in emulation mode too? (i.e. are the long indexed addressing modes available, and not truncated to bank 0)?

MVN and MVP will work in emulation mode, but are all-but-useless due to the inability to set the registers to 16 bits in emulation mode. Long indirect addressing will work in emulation mode, but not as efficiently, since you would have to adjust your pointers for every 256 bytes copied—you wouldn't be able to use a 16-bit index as you can in native mode. Frankly, you should avoid emulation mode, as it substantially negates the many advantages of using the 65C816.

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PostPosted: Tue Jan 26, 2021 1:40 am 
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fachat wrote:
Would this work in emulation mode too? (i.e. are the long indexed addressing modes available, and not truncated to bank 0)?
Not as fast as MVP/MVN but yes this would work, even in Emulation Mode. Depending on your code, it may be a handicap that, in Emulation Mode, X and Y can only be 8-bit, not 16. And likewise the accumulator... otherwise you could consider using 16-bit A to move *two* bytes for each iteration of the loop. :)

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PostPosted: Tue Jan 26, 2021 8:13 am 
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Indeed, it's handy that many of the '816 opcodes are valid and useful even in emulation mode.

In Beeb816, we disable interrupts and switch to native mode in order to use MVN or MVP. (If the source and destination addresses don't overlap, you can use either.)

(If you have a native-mode interrupt handler, even just a shim to the emulation mode handlers, then you wouldn't need to disable interrupts.)


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PostPosted: Wed Jan 27, 2021 9:23 pm 
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Thanks for the valuable input. In fact I basically forgot (ignored...?) the MVP/MVN. This looks like a real "microcoded" operation here, interesting that it is interruptable. Will certainly have to consider it.

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PostPosted: Fri Jan 29, 2021 7:49 am 
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I believe it's interruptible because it essentially performs a conditional branch to itself after moving each byte. This provides a natural way of resuming execution upon return from the handler.


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PostPosted: Fri Jan 29, 2021 8:24 am 
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fachat wrote:
Thanks for the valuable input. In fact I basically forgot (ignored...?) the MVP/MVN. This looks like a real "microcoded" operation here, interesting that it is interruptable. Will certainly have to consider it.

In Supermon 816, I use MVN to implement the F (memory fill) command. Both MVN and MVP are used to implement the T (memory copy) command. On POC V1.2 running at 20 MHz, both functions operate too quickly to be perceptible to the user.

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