http://www.6502.org/tutorials/6502opcodes.htm

I've read that page, and I must be very confused. The page seems informative, but simply does not contain the information needed to assemble/disassemble. I mean, how many bits comprise the opcode? The fact that there are ~56 instructions would lead me to believe that the first 6 bits of an instruction indicate the opcode, but I can't tell. It doesn't look like the instructions are fixed length.

Somebody please point me to a document that gives enough information to disassemble some 6502 machine code.

Thanks, information is very much appreciated.
brian.

All op codes are 8 bits, making hand assembly and disassembly very easy. Many possible op code byte values are unused on the NMOS 6502. Each instruction takes anywhere from two to seven clock cycles, averaging about 4, depending on various factors like how much you can use ZP (8-bit) addressing as opposed to 16-bit, and how much you use indirect and/or indexed addressing modes. If the addressing mode is implied or there is no operand, the instruction is one byte. If the instruction is immediate or has a ZP operand, the instruction takes two bytes. If the operand is a 16-bit address, then the whole instruction takes three bytes.

The tutorial you are referring to only has the instructions and addressing modes of the original NMOS 6502. The CMOS 65c02 added quite a bit, and the 65816, which has 16-bit registers, 24-bit address bus, and lots of additional instructions and addressing modes, fills up the entire 256-combination table of op codes.

Rockwell's and WDC's 65c02's do have some bit intsructions (SMB, RMB, BBS, and BBR) which have the bit number (0-7) embedded in the op code.

Contrary to what that tutorial says, a clock cycle on the 6502 is the same as a clock period; ie, 1 microsecond at 1 MHz (not 2). Complete reads and writes actually happen in half a cycle, when the phase-2 clock signal is high. Pipelining enables the 6502 to do more than one thing per cycle. For example, ADC #xx takes two cycles to carry out five operations, actually finishing up while the next op code is being fetched.

Note that when the operand is two bytes, the low byte comes first. This has to do with the pipelining that makes the 6502 as efficient as it is. For example, in the instruction LDA 1234,X, where the value in the X register is added to address 1234 to get the effective address to load the accumulator from, the low byte is fetched before the high byte, so the processor can start adding the X register's value before it has the high byte. If there is no carry operation, the entire indexed operation takes only four clocks, which is one microsecond at 4MHz. (I don't think there are any 65c02's being made today that won't do at least 4MHz.) If there is a carry requiring the high byte to be incremented, it takes one additional clock.

Welcome to the forum. Come ask as many questions as you need to. We look forward to your involvement.

Garth

Thanks, that helps a bunch.

6502 instructions will be 1, 2, or 3 bytes long. On 3-byte instructions (instructions with 2-byte operands), the low byte comes first. Is that right? I care because I'm thinking about an emulator.

Thanks again.

> 6502 instructions will be 1, 2, or 3 bytes long. On 3-byte instructions
> (instructions with 2-byte operands), the low byte comes first. Is that
> right?

Yes.

> Thanks again.

Any time. Welcome to the forum. Don't be afraid to ask more questions.

Garth

Hi Garth,

Your previous statement (two posts ago)...

"For example, ADC #xx takes two cycles to carry out five operations, actually finishing up while the next op code is being fetched. "

...has me really confused.

I agree, that I have always read in the general descriptions about the
6502, that it had some pipelining in the bus protocol. However, the
"cycle-by-cycle" descriptions in the data-sheet don't illustrate any
pipelining. Did you observe this from an analyzer trace? Are the
details described in print anywhere?

Please explain?

Thanks,
Bye (and Happy Holidays),

Paul

> However, the "cycle-by-cycle" descriptions in the data-sheet don't
> illustrate any pipelining. Did you observe this from an analyzer trace?
> Are the details described in print anywhere?
>
> Please explain?

Sure.

WDC's datasheet does have some cycle-by-cycle operation information (and I have observed some of it by single-cycling the hardware too), but I got this information from their programming manual, pages 40 and 41.

In the case of the example I gave, the 2-cycle instruction ADC #xx, the processor must:

A. Fetch the op code.
B. interpret the op code
C. Fetch the operand.
D. Add the operand to the accumulator.
E. Put the result back in the accumulator.

The first cycle does step A above, possibly while finishing up another instruction. The second cycle does steps B and C. D and E happen while the op code for the next instruction is being fetched. Address incrementing takes place in the same cycles so it doesn't require extra time. This means that at least four things happen in that cycle: steps D and E, address incrementing, and the fetch of the next op code. If the operand were an address, the address also gets transferred to the address bus without taking extra time, as in LDA $1234. Certain instructions of course cannot be completed while the next op code is being fetched, like an STA, since the address and data busses cannot be storing information to one address and fetching an op code from another address at the same time. The Harvard (sp?) architecture was invented to remedy this, but it comes with its own set of limitations too. Overall, one must admit the 6502 is very efficient even with its Von Neumann architecture.

Garth

Hi Garth,

Thanks for the speedy reply.

I was thinking of pipelining at the bus level (a la prefetch-queue)
as opposed to transparent internal operations of the core.

Also, the OSBORN book about the NMOS 6502 says that the PHASE2
clock couldn't be stretched. I believe that the CMOS version
can have the clock stretched. Interestingly, all of the "blurbs" that
describe the differences between the NMOS and CMOS versions fail
to mention this. What do you think?


Thanks again.

Happy Holidays.

Bye,

Paul

Right. The NMOS 6502's regiesters will lose information if the clock isn't kept moving. I think 100kHz is the slowest most manufacturers would guarantee operation, and that assumes a symmetrical clock; ie, no more than 5 microseconds high or low. The CMOS version however can be held indefinitely with phase 2 high without losing information, and WDC's can be held indefinitely in either state. Before I knew about WDC, I had experimented with single-cycling on a CMOS Rockwell 65c02, having breadboarded a little circuit to give a single low pulse of perhaps a couple of microseconds each time I pushed the button, so I could examine what was on the buses in each cycle, probing one pin at a time, with this external "clock" source connected.

As far as a prefetch queue-- the pipelining does not extend any further ahead than I described. It is not deep pipelining. Processors that do have more look-ahead also require more time to "recover" from a branch unless they also have very sophisticated branch prediction to try to figure out whether or not the branch will be taken, before the fact. The 6502 can test a flag and branch taking only three clocks, or do the instruction and keep going in only two clocks if the branch is not taken. Compare to Microchip's PIC RISC that needs four clocks to test the flag, four more to skip the necessary extra branch instruction if it's not supposed to branch, otherwise eight clocks for the branch, adding up to twelve clocks for the test and branch that the 6502 does in only three.

Garth

Hi Garth,

Thanks. I agree.

Have you looked at SGS's ST7 family?
Its an offshoot of the 6502 architecture, but done as
a microcontroller.

Happy Holidays.

Bye,

Paul

Hi Paul,

I'm interesting in learning more about microcontrollers based around the 6502 architecture. I've heard about offshoots from Mitsubishi and Sunplus. Tell us more about the SGS offerings.

I would like to add support for these chips on 6502.org if information is available and people are interested in using them.

Best Regards,
Mike

_________________
- Mike Naberezny (mike@naberezny.com) http://6502.org

Hi Mike,

Check out the ST7 family here:

http://eu.st.com/stonline/profiles/mcu/index.shtml

I don't think that they take 6502 opcodes but the programmers-
model is very similar. 6502 programmers might be comfortable
with it. Note, I haven't used this family in any designs so I can't
directly endorse it. Mouser carries them by-the-way.

Happy Holidays,

Bye,

Paul

Hi Paul,

Thanks for the info; I'll check them out. From your description they sound similar to Atmel's AVR microcontrollers.

Regards,
Mike

_________________
- Mike Naberezny (mike@naberezny.com) http://6502.org