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 Post subject: RAM test
PostPosted: Fri Jul 26, 2013 1:09 am 
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I heard you could do a ram Test by writing $AA and $55 into ram locations and reading them back, but im a noob and I need to know how to read the ram back, and how to know if the test was a success

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 Post subject: Re: RAM test
PostPosted: Fri Jul 26, 2013 4:19 am 
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James_Parsons wrote:
I heard you could do a ram Test by writing $AA and $55 into ram locations and reading them back, but im a noob and I need to know how to read the ram back, and how to know if the test was a success

What is the goal? For example, do you want to test RAMs separately from the ones on the computer's own buses, like production test, being that if the RAM on the computer's own buses worked initially, it will probably continue to indefinitely? If you want to test the RAM on the computer's own buses, is it to verify the working of the RAM itself, or make sure the address decoding was done right, or something else?

If testing the computer's own memory that it needs to run, make sure that you first read each location and keep it in a register or a known-good RAM location before storing and checking the $55 and $AA, and then restore its original value after the check, and don't allow anything to interrupt that process that might overwrite something without saving and restoring. You can see that stepping on, and not restoring, needed variables, stack locations, etc. would crash the computer at some point.

If you're making an external tester like a peripheral, be sure to put other things on the bus between storing a value and reading it back, otherwise you don't know if you're just reading the same value back stored in the data bus capacitance and the memory wasn't really putting out anything. This is not an issue if you're testing RAM on the computer's own buses, because the data bus will have the values of program instruction op codes and operands between accesses to the location being tested. For my 4Mx8 10ns 5V SRAM module's testing, I store $A5 to one byte and $5A to the next, the go back to the first and read and make sure I get $A5, then read the second and make sure I get $5A. Then bus capacitance cannot fake a successful test. I do it again with $5A & $A5 (ie, flip all bits), so each location gets tested with both values. I have the display showing the address progress and the number of failures found (which so far is 0). I use the 8 bits of a byte variable to record which chips are to be tested, since someone may want a module that is less than fully loaded with all 8.

To answer one of your questions, reading back the values is just a matter of LDA___ or CMP___ (CMP to compare the read-back value with what's in the accumulator to make sure it matches) where what's in the blank ("___") tells the address and addressing mode (which may be indirect).

If you want actual code, it would be helpful if you can answer the questions at the top. We are not in the habit of doing homework for students, but will otherwise give whatever help we can to understand how to accomplish the goal.

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 Post subject: Re: RAM test
PostPosted: Fri Jul 26, 2013 4:45 am 
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James_Parsons wrote:
I heard you could do a ram Test by writing $AA and $55 into ram locations and reading them back, but im a noob and I need to know how to read the ram back, and how to know if the test was a success

As Garth noted, there are several RAM test methods you can use, all of them dependent on the context or system.

The most detailed and slowest test is the walking checkerboard, which stores $01 into a location and then rotates it eight times. The end result following rotation should equal $01. Then the same location is EORed with %11111111 to flip all the bits, resulting in $FE in the test location. Again, the location is rotated 8 times and should produce $FE. Next $A5 (or $5A) is written, read back for verification, rotated 8 times, verified, EORed with %11111111 and verified. If all of these tests succeed then that location is probably good and the MPU would move on to the next location. I use a simplified form of this test in my POC unit, but introduce NOPs between the write and read instructions to give bus capacitance some time to bleed off.

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 Post subject: Re: RAM test
PostPosted: Fri Jul 26, 2013 4:56 am 
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Your "walking checkerboard" method would guarantee that you don't have for example data bus bits 7 and 5 shorted together. It would be good to do a similar thing with the address bus too, but as you said, getting super datailed makes it take longer, and is probably not necessary in most cases.

The bus capacitance and near-zero leakage of CMOS can hold a value for at least milliseconds (which I found out when I was experimenting with the testing of my SRAM module), possibly a lot longer.

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 Post subject: Re: RAM test
PostPosted: Fri Jul 26, 2013 4:47 pm 
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GARTHWILSON wrote:
Your "walking checkerboard" method would guarantee that you don't have for example data bus bits 7 and 5 shorted together. It would be good to do a similar thing with the address bus too, but as you said, getting super datailed makes it take longer, and is probably not necessary in most cases.

There's a similar type of RAM test provided with some Linux distributions. I ran it one time on a box with 8 gigs of RAM and a quad core Opteron. It took the better part of a day to complete. :lol:

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The bus capacitance and near-zero leakage of CMOS can hold a value for at least milliseconds (which I found out when I was experimenting with the testing of my SRAM module), possibly a lot longer.

The single walking bit test would discover that condition.

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