i have problem with hardware, but i may be able to pinpoint it only by software tests, so here it goes
problem is that i need to test 1mb of memory, splitted into 64 banks every 16kb of size. bank switching is provided through port located in main memory address space (say it is d000h) banks appears in window from 4000h to 4FFFh
if i test it in primitive way - filling them all and then reading them back - everything is okay, if i fill one and read it back one by one everything is still okay
problem is that in rare occasions data will go bad, and i don't know what was the cause
i need some better way to test that ram
any ideas?

The first thing to look at is the refresh--is it adequate? Otherwise look at the "Stack Problems" Topic in the Hardware forum for some RAM testing ideas.

Scott

don't know for sure
i did my homework and read that thread.. i'll try diffrent approach - maybe it show something
thanks

be back on this

There can be many reasons for this problem. But, I would suggest first, as it was already posted above, to check the refresh rate. It is probably just a little slow. Another simple check - check the wiring for poor connections or shorts. Remove chips from sockets and reinsert. Also, check the +5VDC (if that is what the board is using) power to all chips, some traces may have lower voltage due to high current through a trace or wire, expecially during transitions. Try to solder some +5V and Ground jumpers from voltage regulators or from power connector to the opposite side of the board to make the power distribution better.
Good luck,
Icy.

Are there a sufficent number of refresh addresses in use ? 1M requires 1024 row refresh I think. Check the ram datasheets, sometimes the refresh isn't symmetrical.


Don't rely on this. Bus capacitance may hold the value that gets written until it is read back. It might not even have be written to the ram, but depending on the circuit.



The first dram circuit I worked on, I didn't supply sufficient bypass capacitors and I would get corrupted data. Is the power supply and bypassing ok ?

How is the ram interfaced ? Are there series damping resistors, quite often needed with drams.

What I do to test ram is write an alternating checkerboard pattern to memory, first writing to all of the memory. On a second pass the pattern is read back. So there is a good deal of time that passes between when a cell is written and when it is read. The checkerboard pattern helps detect things like exchanged address / data lines. I write 55 AA 55 AA... hex. Read it back. Then repeat the process but starting with AA 55 AA 55.....


Rob

i got some results when randomizing a bit
firstly i fill banks with pattern from 00 to FF xored with bank number, then after a while i start to read them back switching to random banks and checking what is there
sometimes banks are swapped, so i guess this is capitance of address lines or marginal/poor address multiplexing
every address line is terminated with 33 ohm resistor, but as a output multiplexer i use 74F157 chips - may this be a problem? bus speed is close to 2mhz

I know very little about DRAM, but let me make a couple of comments.

> Don't rely on this. Bus capacitance may hold the value that gets written
> until it is read back. It might not even have be written to the ram, but
> depending on the circuit.

Isn't the data bus shared directly with ROM, without transceivers? If so, the op code and operand bytes for the LDA (addr) will definitely change what's on the data bus (three times!) so its capacitance cannot still be holding the value you just wrote to the DRAM.

> every address line is terminated with 33 ohm resistor, but as a output
> multiplexer i use 74F157 chips - may this be a problem?

"Terminating" specifically means putting the resistive load from the line to ground and possibly another one to power as well. If that's what you're doing, I'd say the load is much too heavy. How much current is it drawing? Rob referred to putting resistors in series, not parallel.

SRAM ICs up to 512Kx8 (4Mb, or half a megabyte) are cheap enough these days however that there may not be any point in using DRAM unless you want at least a megabyte (unlikely with a 6502 project). The SRAMs don't require any special support circuitry (like DRAM controllers) to use, they're simpler, generally faster, and take a fraction as much power. They save board space, assembly labor, and money in a smaller power supply and not having to buy the DRAM controller. SRAMs can also be battery-backed to retain the data when the computer is off.

Garth, i'm really need this megabyte
if anyone wants to look on discussed circuit its here:
http://alan.umcs.lublin.pl/~candle/atari/simm/
and i'm planning to do next project using full address space avial for '816 so drams are my only option
anyway - i'm sorry i mislead you writing about "terminating ttl line" - this what they called it in som polish literature - i was writing of putting 33R resistor in series with address/data line