6502.org Forum  Projects  Code  Documents  Tools  Forum
It is currently Mon May 06, 2024 7:11 pm

All times are UTC




Post new topic Reply to topic  [ 6 posts ] 
Author Message
 Post subject: 65816 Semaphores
PostPosted: Sun Sep 27, 2015 12:32 am 
Offline
User avatar

Joined: Sun Dec 29, 2002 8:56 pm
Posts: 449
Location: Canada
What is your favorite way to implement semaphores with the 65816 processor ? I came up with a scheme for semaphore vars using address reservations which is my preferred approach. It uses a block of memory with a hidden 17th bit to indicate reservation status and a little bit of external hardware.
I haven't actually tried this yet, but it seems like it could work.

Code:
; Uses a 8k page of memory at $FE0000 to $FE1FFF to store 2047 semaphores
; Semaphores are 16 bit vars. The memory actually has a hidden 17th bit
; which is the reservation flag. The reservation flag is set by loading
; from a semaphore. The reservation flag is cleared by storing to the
; semaphore. IF the reservation bit is clear while attempting a store to
; a semaphore, the store fails and the semaphore is not updated.
; The last word of the memory ($FE0FFE) indicates if the last store to a
; semaphore was successful.
; Memory addresses from $FE1000 to $FE1FFF reflect the raw value in the
; semaphore and are an alias for addresses $FE0000 to $FE0FFF. However
; accessing $FE1xxx with a store is always successful and access with a
; load does not set a reservation.
;
; Lock semaphore
; .X = semaphore to lock
; .Y = #retries must be > 0
;
SEMABASE      = $FE0000
STORESUCCESS   = $FE0FFE

LockSemaphore:
.retry:
   DEY
   BMI   .fail
   LDA SEMABASE,X      ; load and reserve
   BEQ   .0002         ; branch if semaphore not set
   CMP TasknoVar      ; semaphore was set, see if by same task
   BEQ   .0003         ; branch if same task
.0002:
   LDA TasknoVar
   STA SEMABASE,X      ; conditional store and clear reservation
   LDA STORESUCCESS   ; get successful store bit
   BEQ .retry         ; branch if store failed
.0003:
   LDA   #1            ; sucessfully locked semaphore
   RTS
.fail:               ; failed to lock semaphore
   LDA   #0
   RTS


; Unlock semaphore
; .X = semaphore to unlock
;
UnlockSemaphore:
   LDA   #$0000         ; set semaphore to zero
   STA SEMABASE,X      ; this will clear any reservation
   RTS

UnlockAllSemaphores:
   LDA   #$0000
   TAX
.loop:
   STA   SEMABASE+$1000,X   ; access the raw values, store never fails
   INX
   INX
   CPX   #$0FFE
   BNE .loop
   RTS

_________________
http://www.finitron.ca


Top
 Profile  
Reply with quote  
 Post subject: Re: 65816 Semaphores
PostPosted: Sun Sep 27, 2015 4:15 am 
Offline
User avatar

Joined: Thu May 28, 2009 9:46 pm
Posts: 8175
Location: Midwestern USA
Rob Finch wrote:
What is your favorite way to implement semaphores with the 65816 processor? I came up with a scheme for semaphore vars using address reservations which is my preferred approach.

How would you prevent contention between two processes for the same semaphore?

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!


Top
 Profile  
Reply with quote  
 Post subject: Re: 65816 Semaphores
PostPosted: Sun Sep 27, 2015 4:44 am 
Offline
User avatar

Joined: Sun Jun 30, 2013 10:26 pm
Posts: 1928
Location: Sacramento, CA, USA
It has been many, many years since I superficially studied the subject, but I was under the impression that an atomic read-modify-write instruction would be sufficient, although it would have to be something that set flags based on the initial value of the semaphore, not the final value like ROL or ASL ... something like the '816's TRB and TSB instructions. Am I way off-track?

The idea is to have an "available" (flag) bit in the semaphore that when set, means it is in use. A process does a "test-and-set" on that (flag) bit, and uses the result of the initial test to see if it was able to acquire the semaphore (the bit went from clear to set) or just got rejected (set to set).

Mike B.


Top
 Profile  
Reply with quote  
 Post subject: Re: 65816 Semaphores
PostPosted: Sun Sep 27, 2015 5:47 am 
Offline
User avatar

Joined: Sun Dec 29, 2002 8:56 pm
Posts: 449
Location: Canada
Quote:
something like the '816's TRB and TSB instructions. Am I way off-track?

You are on-track. One of the reasons address reservations are my favorite are they don't have to respect a bus cycle lock. In my simple system the bus isn't locked for RMW operations. Another master may take over in the middle of a RMW operation. It only matters if the same address is being written by both masters.

Quote:
How would you prevent contention between two processes for the same semaphore?

I am not quite sure I understand the question. But, I think contention may be prevented by clearing the semaphore reservations during an interrupt routine. Only one process can run at one time (on a single processor). Two different processes can try and acquire the same semaphore only if a process is interrupted during the acquisition. The semaphore acquisition will fail if a second process tries to obtain it because the reservation has been cleared.

A dedicated signal may be required to clear all the hidden reservation bits, otherwise too much time would be spent clearing reservations during an interrupt.

_________________
http://www.finitron.ca


Top
 Profile  
Reply with quote  
 Post subject: Re: 65816 Semaphores
PostPosted: Sun Sep 27, 2015 6:17 am 
Offline

Joined: Sat Jul 28, 2012 11:41 am
Posts: 442
Location: Wiesbaden, Germany
I used INC & DEC memory to lock an enabled interrupt driver on the 6502.
1 = unlocked, <1 signed = locked
Decrement to lock, Z=1 succeeeded, N=1 failed, increment on failed lock (or count the number of failed attempts)
Increment or store 1 to unlock (I used increment and repeat the driver until Z=0 and N=0, background fill of a buffer)

However, this would not work with multiple CPUs accessing the bus. MP capable CPUs need to have serialized instructions locking the memory bus for these instructions. CPUs with cache also need to purge the address from all buffers.

_________________
6502 sources on GitHub: https://github.com/Klaus2m5


Top
 Profile  
Reply with quote  
 Post subject: Re: 65816 Semaphores
PostPosted: Sun Sep 27, 2015 11:47 am 
Offline
User avatar

Joined: Sun Dec 29, 2002 8:56 pm
Posts: 449
Location: Canada
Quote:
I used INC & DEC memory to lock an enabled interrupt driver on the 6502.
1 = unlocked, <1 signed = locked
Decrement to lock, Z=1 succeeeded, N=1 failed, increment on failed lock (or count the number of failed attempts)
Increment or store 1 to unlock (I used increment and repeat the driver until Z=0 and N=0, background fill of a buffer)

I sometimes wish the 6502 had saturating increment and decrement instructions to make it a little easier for semaphores.

Bus locking instructions take the lead in popularity.

_________________
http://www.finitron.ca


Top
 Profile  
Reply with quote  
Display posts from previous:  Sort by  
Post new topic Reply to topic  [ 6 posts ] 

All times are UTC


Who is online

Users browsing this forum: No registered users and 6 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to: