Quote:
Zero page indirect indexed will also be unsigned and truncated to zero page for the pointer value.
This definitely is true for the 6502.
However, the 65816 in native-mode behaves differently, if memory serves me correctly. Since direct-page can now float freely anywhere in bank 0, I believe that if X=$F0 and you access $F0,X, you will actually access location (D+$1E0) & 0xFFFF, where D is the current address stored in the direct page register.
So, for the benefit of folks reading this forum, particularly those new to the "Terbium" architecture, it would be most helpful to qualify which CPUs you're asking about.