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PostPosted: Wed Aug 25, 2010 2:22 am 
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Joined: Fri Dec 11, 2009 3:50 pm
Posts: 3367
Location: Ontario, Canada
dclxvi wrote:
[65C02] NOPs can also be used for this purpose

True, and no processor status flags are affected. Just bear in mind that one important issue (first mentioned on page 1 of this thread) remains: the danger of a Destructive Read -- an inadvertent access to an IO device.

65C02 "NOPs" include several Read operations for which the fetched data is ignored by the CPU. But the transaction is 100% genuine as far as the external bus is concerned, and therefore the danger remains. Interestingly, the new NOPs on the 'C02 employ Immediate, Absolute, Z-Pg and Z-Pg,X address modes, as explained here.

Use of 65C02 NOP's for our skip-a-byte trick is therefore restricted -- not only to 65C02 systems, but also to systems which don't have read-sensitive IO registers mapped to any of the addresses which may be affected.

-- Jeff


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PostPosted: Sat Oct 02, 2010 10:05 pm 
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Joined: Tue Jul 05, 2005 7:08 pm
Posts: 1043
Location: near Heidelberg, Germany
I just found an interesting alternative to skipping an opcode (from http://www.6502.org/tutorials/65c02opcodes.html - even on 6502.org :-):
Code:
CLEAR_FLAG CLC
           DB  $B0
SET_FLAG   SEC
           ROR FLAG

Quote from the page:
Quote:
When entering via CLEAR_FLAG, the $B0 becomes a 2-cycle BCS instruction, which is not taken (since the carry is clear). Since BCS does not affect any flags, it serves, in this situation, as a two byte, two cycle NOP and provides a subtle, but useful way to efficiently skip the SEC instruction. However, using a branch instruction to skip a one byte instruction requires a flag value to be known beforehand (so that the branch won't be taken).

The page discusses even more options using the extra NOP opcodes of the 65C02.

André


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