BigDumbDinosaur wrote:
banedon wrote:
I've attached the entire PLD file here: (re-uploaded)
Ah, yes, I recall now. Then, as now, I recommended you not use Ø2 in decoding equations. Also, assuming this is for use with the 65C816, you aren't accounting for VDA and VPA. Plus I don't understand the bank setup you're using.This particular design is a 65c02. I was working on two designs at the same time: 6502 and 65816. I finished the '02 first, so got a PCB fabbed just before Christmas. Once I've finished with it, it's back to the 65816 design which does test for VDA & VDA in the CPLD (the one in the '02 and one I the 816 are very similar, but not quite the same). It's been slowed down a bit as I've been learning how to use Kicad over Christmas, so am remaking the 65816 design in there as I won't be restircted to a 160x100mm (an Eagle maximum, restricted by my old license).